Design and Implementation of Power Efficient 10-Bit Dual Port SRAM on 28 nm Technology.
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| Title: | Design and Implementation of Power Efficient 10-Bit Dual Port SRAM on 28 nm Technology. |
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| Authors: | Gulati, Anmol1 anmol.gulati09@gmail.com, Gupta, Ashutosh2 agupta5@amity.edu, Murgai, Shruti1 shrutimurgai@gmail.com, Bhaskar, Lala2 lbhaskar1@amity.edu |
| Source: | AIP Conference Proceedings. 2016, Vol. 1715 Issue 1, p020002-1-020002-8. 8p. 3 Color Photographs, 6 Diagrams, 5 Charts, 2 Graphs. |
| Database: | Academic Search Ultimate |
| ISSN: | 0094243X |
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| DOI: | 10.1063/1.4942684 |
