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Design and Implementation of Power Efficient 10-Bit Dual Port SRAM on 28 nm Technology.

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Title: Design and Implementation of Power Efficient 10-Bit Dual Port SRAM on 28 nm Technology.
Authors: Gulati, Anmol1 anmol.gulati09@gmail.com, Gupta, Ashutosh2 agupta5@amity.edu, Murgai, Shruti1 shrutimurgai@gmail.com, Bhaskar, Lala2 lbhaskar1@amity.edu
Source: AIP Conference Proceedings. 2016, Vol. 1715 Issue 1, p020002-1-020002-8. 8p. 3 Color Photographs, 6 Diagrams, 5 Charts, 2 Graphs.
Database: Academic Search Ultimate
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Header DbId: asn
DbLabel: Academic Search Ultimate
An: 113709076
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PubType: Conference
PubTypeId: conference
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  Data: Design and Implementation of Power Efficient 10-Bit Dual Port SRAM on 28 nm Technology.
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  Data: <searchLink fieldCode="JN" term="%22AIP+Conference+Proceedings%22">AIP Conference Proceedings</searchLink>. 2016, Vol. 1715 Issue 1, p020002-1-020002-8. 8p. 3 Color Photographs, 6 Diagrams, 5 Charts, 2 Graphs.
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=asn&AN=113709076
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        Value: 10.1063/1.4942684
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      – Code: eng
        Text: English
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      – TitleFull: Design and Implementation of Power Efficient 10-Bit Dual Port SRAM on 28 nm Technology.
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            NameFull: Gulati, Anmol
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            NameFull: Gupta, Ashutosh
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            NameFull: Murgai, Shruti
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              Text: 2016
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