APA (7th ed.) Citation

Neeraj, Goel, A., Sharma, S., Rewari, S., & Gupta, R. S. (2022). SiC‐based analytical model for gate‐stack dual metal nanowire FET with enhanced analog performance. International Journal of Numerical Modelling, 35(4), 1. https://doi.org/10.1002/jnm.2986

Chicago Style (17th ed.) Citation

Neeraj, Anubha Goel, Shobha Sharma, Sonam Rewari, and Radhey Shyam Gupta. "SiC‐based Analytical Model for Gate‐stack Dual Metal Nanowire FET with Enhanced Analog Performance." International Journal of Numerical Modelling 35, no. 4 (2022): 1. https://doi.org/10.1002/jnm.2986.

MLA (9th ed.) Citation

Neeraj, et al. "SiC‐based Analytical Model for Gate‐stack Dual Metal Nanowire FET with Enhanced Analog Performance." International Journal of Numerical Modelling, vol. 35, no. 4, 2022, p. 1, https://doi.org/10.1002/jnm.2986.