SiC‐based analytical model for gate‐stack dual metal nanowire FET with enhanced analog performance.
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| Title: | SiC‐based analytical model for gate‐stack dual metal nanowire FET with enhanced analog performance. |
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| Authors: | Neeraj1 (AUTHOR), Goel, Anubha2 (AUTHOR), Sharma, Shobha1 (AUTHOR), Rewari, Sonam3 (AUTHOR) rewarisonam@gmail.com, Gupta, Radhey Shyam2 (AUTHOR) |
| Source: | International Journal of Numerical Modelling. Jul2022, Vol. 35 Issue 4, p1-15. 15p. |
| Database: | Academic Search Ultimate |
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| ISSN: | 08943370 |
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| DOI: | 10.1002/jnm.2986 |
