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Design and optimization of a quaternary booth multiplier in quaternary logic using carbon nanotube transistors.

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Title: Design and optimization of a quaternary booth multiplier in quaternary logic using carbon nanotube transistors.
Authors: toosanloo, Sobhan Aghamalizadeh1 (AUTHOR), javidan, javad1 (AUTHOR) javidan@uma.ac.ir
Source: Scientific Reports. 10/14/2025, Vol. 15 Issue 1, p1-18. 18p.
Database: Academic Search Ultimate
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  Data: <searchLink fieldCode="JN" term="%22Scientific+Reports%22">Scientific Reports</searchLink>. 10/14/2025, Vol. 15 Issue 1, p1-18. 18p.
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        Value: 10.1038/s41598-025-19704-1
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