PyHLS: Intermediate Representation for Versatile High-Level Synthesis.
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| Title: | PyHLS: Intermediate Representation for Versatile High-Level Synthesis. |
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| Authors: | Cieszewski, Radoslaw1 radoslaw.cieszewski@pw.edu.pl |
| Source: | International Journal of Electronics & Telecommunications. 2025, Vol. 71 Issue 4, p1-7. 9p. |
| Database: | Academic Search Ultimate |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=asn&AN=189126966 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.24425/ijet.2025.156531 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 1 Titles: – TitleFull: PyHLS: Intermediate Representation for Versatile High-Level Synthesis. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Cieszewski, Radoslaw IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 10 Text: 2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 20818491 Numbering: – Type: volume Value: 71 – Type: issue Value: 4 Titles: – TitleFull: International Journal of Electronics & Telecommunications Type: main |
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