APA (7th ed.) Citation

Saravanan, M., Parthasarathy, E., Rahi, S. B., & Natarajan, R. (2025). Impact of drain and source engineering on dual metal InAs-GaSb VTFETs with high-K gate stack design. Scientific Reports, 15(1), 1. https://doi.org/10.1038/s41598-025-28448-x

Chicago Style (17th ed.) Citation

Saravanan, M., Eswaran Parthasarathy, Shiromani Balmukund Rahi, and Ramkumar Natarajan. "Impact of Drain and Source Engineering on Dual Metal InAs-GaSb VTFETs with High-K Gate Stack Design." Scientific Reports 15, no. 1 (2025): 1. https://doi.org/10.1038/s41598-025-28448-x.

MLA (9th ed.) Citation

Saravanan, M., et al. "Impact of Drain and Source Engineering on Dual Metal InAs-GaSb VTFETs with High-K Gate Stack Design." Scientific Reports, vol. 15, no. 1, 2025, p. 1, https://doi.org/10.1038/s41598-025-28448-x.