APA (7th ed.) Citation

Gupta, T., Verma, G., & Akhter, S. (2023). Performance Analysis of a Generic Modular Adder via RTL Programming and IP Modeling Techniques on FPGA. Ingénierie des Systèmes d'Information, 28(5), 1255. https://doi.org/10.18280/isi.280514

Chicago Style (17th ed.) Citation

Gupta, Tukur, Gaurav Verma, and Shamim Akhter. "Performance Analysis of a Generic Modular Adder via RTL Programming and IP Modeling Techniques on FPGA." Ingénierie Des Systèmes D'Information 28, no. 5 (2023): 1255. https://doi.org/10.18280/isi.280514.

MLA (9th ed.) Citation

Gupta, Tukur, et al. "Performance Analysis of a Generic Modular Adder via RTL Programming and IP Modeling Techniques on FPGA." Ingénierie Des Systèmes D'Information, vol. 28, no. 5, 2023, p. 1255, https://doi.org/10.18280/isi.280514.