APA (7th ed.) Citation

Shinde, V., Karpude, Z., Kolhe, P., & Wadte, A. (2025). Design and Simulation of 32-Bit RISC Architecture Based on MIPS using Verilog. International Scientific Journal of Engineering & Management, 4(3), 1. https://doi.org/10.55041/ISJEM02553

Chicago Style (17th ed.) Citation

Shinde, Vaishnavi, Zeba Karpude, Pooja Kolhe, and Alpesh Wadte. "Design and Simulation of 32-Bit RISC Architecture Based on MIPS Using Verilog." International Scientific Journal of Engineering & Management 4, no. 3 (2025): 1. https://doi.org/10.55041/ISJEM02553.

MLA (9th ed.) Citation

Shinde, Vaishnavi, et al. "Design and Simulation of 32-Bit RISC Architecture Based on MIPS Using Verilog." International Scientific Journal of Engineering & Management, vol. 4, no. 3, 2025, p. 1, https://doi.org/10.55041/ISJEM02553.