FPGA Hardware Accelerators - Case Study on Design Methodologies and Trade-Offs
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| Title: | FPGA Hardware Accelerators - Case Study on Design Methodologies and Trade-Offs |
|---|---|
| Authors: | Ryan, Matthew V |
| Committee Members: | Marcin Lukowiak |
| Summary: | Previous research has shown that the performance of any computation is directly related to the architecture on which it is performed. As a result, the performance of compute intensive applications can be improved using heterogeneous systems. These systems consist of various processor architectures such as CPU, FPGA, DSP, and GPU. Individual computations can be performed in parallel on different processor architecrues within the heterogeneous system. Computations are performed by utilizing existing designs from implementation libraries. There is a lack of FPGA accelerators for use in these libraries and as such additional implementations need to be designed. Different design methodologies for developing FPGA accelerators result in implementations that vary in performance, design time, and resource utilization. A particular method and supporting toolset may produce better results for one type of design than another. The customary method for designing FPGA accelerators is to develop the system architecture from an algorithm and model it using a hardware decription language (HDL). Another method is to convert directly from a software implementation to HDL. This process is known as high level synthesis (HLS). The advantages and disadvantages of these two techniques can be examined through comparison of different linear algebra operations. Many linear algebra operations are parallel in nature which makes them potentially good choices to speedup through implementation on an FPGA. In particular, matrix multiplication is an excellent candidate for examination due to not only its parallelism but also its multitude of different algorithms. The goal of this research is to design different matrix multiplication accelerators and provide insight into the advantages and disadvantages of each design procedure. |
| URL: | https://scholarworks.rit.edu/theses/959 |
| Database: | OpenDissertations |
| FullText | Text: Availability: 0 |
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| Header | DbId: ddu DbLabel: OpenDissertations An: ddu.oai.scholarworks.rit.edu.theses.1963 AccessLevel: 6 PubType: Dissertation/ Thesis PubTypeId: dissertation PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: FPGA Hardware Accelerators - Case Study on Design Methodologies and Trade-Offs – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ryan%2C+Matthew+V%22">Ryan, Matthew V</searchLink> – Name: Author Label: Committee Members Group: Au Data: <searchLink fieldCode="CO" term="%22Marcin+Lukowiak%22">Marcin Lukowiak</searchLink> – Name: Abstract Label: Summary Group: Ab Data: Previous research has shown that the performance of any computation is directly related to the architecture on which it is performed. As a result, the performance of compute intensive applications can be improved using heterogeneous systems. These systems consist of various processor architectures such as CPU, FPGA, DSP, and GPU. Individual computations can be performed in parallel on different processor architecrues within the heterogeneous system. Computations are performed by utilizing existing designs from implementation libraries. There is a lack of FPGA accelerators for use in these libraries and as such additional implementations need to be designed. Different design methodologies for developing FPGA accelerators result in implementations that vary in performance, design time, and resource utilization. A particular method and supporting toolset may produce better results for one type of design than another. The customary method for designing FPGA accelerators is to develop the system architecture from an algorithm and model it using a hardware decription language (HDL). Another method is to convert directly from a software implementation to HDL. This process is known as high level synthesis (HLS). The advantages and disadvantages of these two techniques can be examined through comparison of different linear algebra operations. Many linear algebra operations are parallel in nature which makes them potentially good choices to speedup through implementation on an FPGA. In particular, matrix multiplication is an excellent candidate for examination due to not only its parallelism but also its multitude of different algorithms. The goal of this research is to design different matrix multiplication accelerators and provide insight into the advantages and disadvantages of each design procedure. – Name: URL Label: URL Group: URL Data: <link linkTarget="URL" linkTerm="https://scholarworks.rit.edu/theses/959" linkWindow="_blank">https://scholarworks.rit.edu/theses/959</link> |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=ddu&AN=ddu.oai.scholarworks.rit.edu.theses.1963 |
| RecordInfo | BibRecord: BibEntity: Languages: – Code: eng Text: English Subjects: – SubjectFull: FPGA Type: general – SubjectFull: HDL Type: general – SubjectFull: Reconfigurable Type: general – SubjectFull: Field programmable gate arrays--Design and construction Type: general – SubjectFull: Computer input-output equipment--Design and construction Type: general – SubjectFull: High performance computing Type: general – SubjectFull: Electronic Devices and Semiconductor Manufacturing Type: general Titles: – TitleFull: FPGA Hardware Accelerators - Case Study on Design Methodologies and Trade-Offs Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ryan, Matthew V IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Type: published Y: 2013 |
| ResultId | 1 |
