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A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.

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Title: A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.
Authors: Zhu, Jianfeng1, Pan, Liyang1, Yan, Yaru1, Wu, Dong1, He, Hu1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Dec2014, Vol. 22 Issue 12, p2629-2634. 6p.
Subjects: Field programmable gate arrays, Programmable circuits, Low voltage systems, Energy conservation, Electric capacity
Abstract: Dual supply voltage was a mature method to reduce the dynamic power of specific and programmable circuits, and the unsettled low voltage level (VL) was proved to have impact on its effect. In this paper, a circuit-level power model is developed to estimate the optimal VL fast for field-programmable gate array (FPGA). The model is mainly based on the path delay distribution of applications and the delay function of the integrated circuit technology. It can also count minor factors, such as path overlap, transition density, and capacitance. Experiment was conducted on a 90-nm FPGA model using MCNC benchmark. The results showed that the proposed method could generate near optimum VL for most benchmarks. The best power reduction ratio is only 5.6% less than the gate-level heuristic method, which is relatively precise, but our method is \sim100\--10000 times faster. It implies that the dual voltage design with variable VL is a possible and promising low power method for field-programmable devices. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:Dual supply voltage was a mature method to reduce the dynamic power of specific and programmable circuits, and the unsettled low voltage level (VL) was proved to have impact on its effect. In this paper, a circuit-level power model is developed to estimate the optimal VL fast for field-programmable gate array (FPGA). The model is mainly based on the path delay distribution of applications and the delay function of the integrated circuit technology. It can also count minor factors, such as path overlap, transition density, and capacitance. Experiment was conducted on a 90-nm FPGA model using MCNC benchmark. The results showed that the proposed method could generate near optimum VL for most benchmarks. The best power reduction ratio is only 5.6% less than the gate-level heuristic method, which is relatively precise, but our method is \sim100\--10000 times faster. It implies that the dual voltage design with variable VL is a possible and promising low power method for field-programmable devices. [ABSTRACT FROM AUTHOR]
ISSN:10638210
DOI:10.1109/TVLSI.2013.2296791