A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.
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| Title: | A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA. |
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| Authors: | Zhu, Jianfeng1, Pan, Liyang1, Yan, Yaru1, Wu, Dong1, He, Hu1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Dec2014, Vol. 22 Issue 12, p2629-2634. 6p. |
| Subjects: | Field programmable gate arrays, Programmable circuits, Low voltage systems, Energy conservation, Electric capacity |
| Abstract: | Dual supply voltage was a mature method to reduce the dynamic power of specific and programmable circuits, and the unsettled low voltage level (VL) was proved to have impact on its effect. In this paper, a circuit-level power model is developed to estimate the optimal VL fast for field-programmable gate array (FPGA). The model is mainly based on the path delay distribution of applications and the delay function of the integrated circuit technology. It can also count minor factors, such as path overlap, transition density, and capacitance. Experiment was conducted on a 90-nm FPGA model using MCNC benchmark. The results showed that the proposed method could generate near optimum VL for most benchmarks. The best power reduction ratio is only 5.6% less than the gate-level heuristic method, which is relatively precise, but our method is \sim100\--10000 times faster. It implies that the dual voltage design with variable VL is a possible and promising low power method for field-programmable devices. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Items | – Name: Title Label: Title Group: Ti Data: A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Zhu%2C+Jianfeng%22">Zhu, Jianfeng</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Pan%2C+Liyang%22">Pan, Liyang</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Yan%2C+Yaru%22">Yan, Yaru</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Wu%2C+Dong%22">Wu, Dong</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22He%2C+Hu%22">He, Hu</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Dec2014, Vol. 22 Issue 12, p2629-2634. 6p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Programmable+circuits%22">Programmable circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Low+voltage+systems%22">Low voltage systems</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+conservation%22">Energy conservation</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+capacity%22">Electric capacity</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Dual supply voltage was a mature method to reduce the dynamic power of specific and programmable circuits, and the unsettled low voltage level (VL) was proved to have impact on its effect. In this paper, a circuit-level power model is developed to estimate the optimal VL fast for field-programmable gate array (FPGA). The model is mainly based on the path delay distribution of applications and the delay function of the integrated circuit technology. It can also count minor factors, such as path overlap, transition density, and capacitance. Experiment was conducted on a 90-nm FPGA model using MCNC benchmark. The results showed that the proposed method could generate near optimum VL for most benchmarks. The best power reduction ratio is only 5.6% less than the gate-level heuristic method, which is relatively precise, but our method is \sim100\--10000 times faster. It implies that the dual voltage design with variable VL is a possible and promising low power method for field-programmable devices. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2013.2296791 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 6 StartPage: 2629 Subjects: – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Programmable circuits Type: general – SubjectFull: Low voltage systems Type: general – SubjectFull: Energy conservation Type: general – SubjectFull: Electric capacity Type: general Titles: – TitleFull: A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Zhu, Jianfeng – PersonEntity: Name: NameFull: Pan, Liyang – PersonEntity: Name: NameFull: Yan, Yaru – PersonEntity: Name: NameFull: Wu, Dong – PersonEntity: Name: NameFull: He, Hu IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: Dec2014 Type: published Y: 2014 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 22 – Type: issue Value: 12 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
| ResultId | 1 |
