Steady State and Transient Thermal Analysis of Chip Scale Packages.
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| Title: | Steady State and Transient Thermal Analysis of Chip Scale Packages. |
|---|---|
| Authors: | Chambers, Ben, Lee, Tien-Yu Tom, Blood, William |
| Source: | Journal of Electronics Manufacturing. Jun1999, Vol. 9 Issue 2, p131. 9p. |
| Subjects: | Chip scale packaging, Energy dissipation |
| Abstract: | This paper summarizes a study of chip scale packages (CSP) to determine their maximum allowable power dissipation within typical system level environments. These results can be used to determine the applicability of utilizing CSPs from the standpoint of die power dissipation. Both steady state and transient thermal performance is covered in this study. The steady state portion used in-house software, while closed-form solutions were utilized for the transient analysis. The steady state power limit, while governed by a number of parameters, is dependent mainly upon system level parameters (heatsinking, cooling mode — i.e., natural or forced convection, and PCB power loading). Thermal enhancement features (e.g. thermal vias and bumps) are not generally effective in increasing the maximum power that can be dissipated by the package in the end use environment. The variables investigated in the steady state study included die size, thermal vias and bumps, the addition of a heatsink, natural/forced convection boundary conditions, printed circuit board (PCB) heat loading, and PCB thermal conductivity. The transient portion considered die size, pulse shape and duration, and the addition of a heatsink. For relatively short duration transients (e.g. switching an inductive load), the power limit is governed by the die geometry; magnitude, shape and duration of the heating pulse; and the starting and maximum allowable temperatures of the junction. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Electronics Manufacturing is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 10236875 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Steady State and Transient Thermal Analysis of Chip Scale Packages. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Chambers%2C+Ben%22">Chambers, Ben</searchLink><br /><searchLink fieldCode="AR" term="%22Lee%2C+Tien-Yu+Tom%22">Lee, Tien-Yu Tom</searchLink><br /><searchLink fieldCode="AR" term="%22Blood%2C+William%22">Blood, William</searchLink> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Journal+of+Electronics+Manufacturing%22">Journal of Electronics Manufacturing</searchLink>. Jun1999, Vol. 9 Issue 2, p131. 9p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Chip+scale+packaging%22">Chip scale packaging</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+dissipation%22">Energy dissipation</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This paper summarizes a study of chip scale packages (CSP) to determine their maximum allowable power dissipation within typical system level environments. These results can be used to determine the applicability of utilizing CSPs from the standpoint of die power dissipation. Both steady state and transient thermal performance is covered in this study. The steady state portion used in-house software, while closed-form solutions were utilized for the transient analysis. The steady state power limit, while governed by a number of parameters, is dependent mainly upon system level parameters (heatsinking, cooling mode — i.e., natural or forced convection, and PCB power loading). Thermal enhancement features (e.g. thermal vias and bumps) are not generally effective in increasing the maximum power that can be dissipated by the package in the end use environment. The variables investigated in the steady state study included die size, thermal vias and bumps, the addition of a heatsink, natural/forced convection boundary conditions, printed circuit board (PCB) heat loading, and PCB thermal conductivity. The transient portion considered die size, pulse shape and duration, and the addition of a heatsink. For relatively short duration transients (e.g. switching an inductive load), the power limit is governed by the die geometry; magnitude, shape and duration of the heating pulse; and the starting and maximum allowable temperatures of the junction. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Journal of Electronics Manufacturing is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1142/S0960313199000064 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 131 Subjects: – SubjectFull: Chip scale packaging Type: general – SubjectFull: Energy dissipation Type: general Titles: – TitleFull: Steady State and Transient Thermal Analysis of Chip Scale Packages. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Chambers, Ben – PersonEntity: Name: NameFull: Lee, Tien-Yu Tom – PersonEntity: Name: NameFull: Blood, William IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun1999 Type: published Y: 1999 Identifiers: – Type: issn-print Value: 09603131 Numbering: – Type: volume Value: 9 – Type: issue Value: 2 Titles: – TitleFull: Journal of Electronics Manufacturing Type: main |
| ResultId | 1 |
