A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer.
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| Title: | A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer. |
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| Authors: | Harikumar, Prakash1 prakash.harikumar@liu.se, Wikner, J. Jacob1 jacob.wikner@liu.se |
| Source: | Integration: The VLSI Journal. Jun2015, Vol. 50, p28-38. 11p. |
| Subjects: | Successive approximation analog-to-digital converters, Complementary metal oxide semiconductors, Analog-to-digital converters, Binary number system, Topology |
| Abstract: | This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm 2 . [ABSTRACT FROM AUTHOR] |
| Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 103000771 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Harikumar%2C+Prakash%22">Harikumar, Prakash</searchLink><relatesTo>1</relatesTo><i> prakash.harikumar@liu.se</i><br /><searchLink fieldCode="AR" term="%22Wikner%2C+J%2E+Jacob%22">Wikner, J. Jacob</searchLink><relatesTo>1</relatesTo><i> jacob.wikner@liu.se</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Integration%3A+The+VLSI+Journal%22">Integration: The VLSI Journal</searchLink>. Jun2015, Vol. 50, p28-38. 11p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Successive+approximation+analog-to-digital+converters%22">Successive approximation analog-to-digital converters</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Analog-to-digital+converters%22">Analog-to-digital converters</searchLink><br /><searchLink fieldCode="DE" term="%22Binary+number+system%22">Binary number system</searchLink><br /><searchLink fieldCode="DE" term="%22Topology%22">Topology</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm 2 . [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.vlsi.2015.01.002 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 11 StartPage: 28 Subjects: – SubjectFull: Successive approximation analog-to-digital converters Type: general – SubjectFull: Complementary metal oxide semiconductors Type: general – SubjectFull: Analog-to-digital converters Type: general – SubjectFull: Binary number system Type: general – SubjectFull: Topology Type: general Titles: – TitleFull: A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Harikumar, Prakash – PersonEntity: Name: NameFull: Wikner, J. Jacob IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun2015 Type: published Y: 2015 Identifiers: – Type: issn-print Value: 01679260 Numbering: – Type: volume Value: 50 Titles: – TitleFull: Integration: The VLSI Journal Type: main |
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