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An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling.

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Title: An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling.
Authors: Yao, Jian1, Ye, Zuochang1, Wang, Yan1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jul2015, Vol. 23 Issue 7, p1245-1253. 9p.
Subjects: Static random access memory chips, Integrated memory circuits, Static random access memory, IEEE 802.16 (Standard), Ethernet, IEEE 802 standard
Abstract: SRAM cells usually require extremely low failure rate or equivalently extremely high production yield, making it impractical to perform yield analysis using Monte Carlo (MC) method as huge amount of samples are needed. Fast MC methods, e.g., importance sampling methods, are still too expensive as the anticipated failure rate is very low. In this paper, a new SRAM yield analysis method is proposed to tackle this issue. The key idea is to improve traditional importance sampling method with an efficient online surrogate model. Experimental results show that the proposed yield analysis method achieves $5\times $ – $22\times $ speedup over existing state-of-the-art techniques without sacrificing estimation accuracy. Sigma distribution and schmoo plot can be quickly generated by the proposed method, which is very useful for realistic applications. Based on the proposed yield analysis method, an efficient yield optimization method has been developed to further automate the SRAM cell design procedure where process variations can be fully considered. Experimental results show that a fully automatic yield optimization for SRAM cells can be done within only a few hours. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling.
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  Data: <searchLink fieldCode="DE" term="%22Static+random+access+memory+chips%22">Static random access memory chips</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+memory+circuits%22">Integrated memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Static+random+access+memory%22">Static random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22IEEE+802%2E16+%28Standard%29%22">IEEE 802.16 (Standard)</searchLink><br /><searchLink fieldCode="DE" term="%22Ethernet%22">Ethernet</searchLink><br /><searchLink fieldCode="DE" term="%22IEEE+802+standard%22">IEEE 802 standard</searchLink>
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  Data: SRAM cells usually require extremely low failure rate or equivalently extremely high production yield, making it impractical to perform yield analysis using Monte Carlo (MC) method as huge amount of samples are needed. Fast MC methods, e.g., importance sampling methods, are still too expensive as the anticipated failure rate is very low. In this paper, a new SRAM yield analysis method is proposed to tackle this issue. The key idea is to improve traditional importance sampling method with an efficient online surrogate model. Experimental results show that the proposed yield analysis method achieves $5\times $ – $22\times $ speedup over existing state-of-the-art techniques without sacrificing estimation accuracy. Sigma distribution and schmoo plot can be quickly generated by the proposed method, which is very useful for realistic applications. Based on the proposed yield analysis method, an efficient yield optimization method has been developed to further automate the SRAM cell design procedure where process variations can be fully considered. Experimental results show that a fully automatic yield optimization for SRAM cells can be done within only a few hours. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TVLSI.2014.2336851
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        Text: English
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      – SubjectFull: Integrated memory circuits
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      – SubjectFull: Static random access memory
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              Text: Jul2015
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