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Low cost fault-tolerant routing algorithm for Networks-on-Chip.

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Title: Low cost fault-tolerant routing algorithm for Networks-on-Chip.
Authors: Liu, Junxiu1 liu-j4@email.ulster.ac.uk, Harkin, Jim1 jg.harkin@ulster.ac.uk, Li, Yuhua2 y.li@salford.ac.uk, Maguire, Liam1 lp.maguire@ulster.ac.uk
Source: Microprocessors & Microsystems. Aug2015, Vol. 39 Issue 6, p358-372. 15p.
Subjects: Fault-tolerant computing, Routing algorithms, Networks on a chip, Adaptive computing systems, Real-time computing
Abstract: A novel adaptive routing algorithm – Efficient Dynamic Adaptive Routing (EDAR) is proposed to provide a fault-tolerant capability for Networks-on-Chip (NoC) via an efficient routing path selection mechanism. It is based on a weighted path selection strategy, which exploits the status of real-time NoC traffic made available via monitor modules. The key performance goal is to maintain throughput under congested and faulty conditions via effective routing path decisions. In the proposed EDAR, port weights are calculated in real-time according to the channel status – Idle/Busy/Congested/Faulty, and the port with the lowest weighting is ranked as the near-optimal route to forward packets. This mechanism enables the router to bypass congested ports and tolerate faulty ports. To assess the latency and throughput of the proposed routing algorithm, several traffic patterns for both fault-free and faulty NoCs were evaluated. Results show that EDAR can achieve higher throughput compared to other state of the art routing algorithms under various traffic patterns and levels of injected faults. In addition, the hardware area overhead for EDAR is demonstrated to have a reasonably low cost which maintains scalability for large NoC implementations. [ABSTRACT FROM AUTHOR]
Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 103654418
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PubType: Academic Journal
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  Data: <searchLink fieldCode="DE" term="%22Fault-tolerant+computing%22">Fault-tolerant computing</searchLink><br /><searchLink fieldCode="DE" term="%22Routing+algorithms%22">Routing algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Networks+on+a+chip%22">Networks on a chip</searchLink><br /><searchLink fieldCode="DE" term="%22Adaptive+computing+systems%22">Adaptive computing systems</searchLink><br /><searchLink fieldCode="DE" term="%22Real-time+computing%22">Real-time computing</searchLink>
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  Data: A novel adaptive routing algorithm – Efficient Dynamic Adaptive Routing (EDAR) is proposed to provide a fault-tolerant capability for Networks-on-Chip (NoC) via an efficient routing path selection mechanism. It is based on a weighted path selection strategy, which exploits the status of real-time NoC traffic made available via monitor modules. The key performance goal is to maintain throughput under congested and faulty conditions via effective routing path decisions. In the proposed EDAR, port weights are calculated in real-time according to the channel status – Idle/Busy/Congested/Faulty, and the port with the lowest weighting is ranked as the near-optimal route to forward packets. This mechanism enables the router to bypass congested ports and tolerate faulty ports. To assess the latency and throughput of the proposed routing algorithm, several traffic patterns for both fault-free and faulty NoCs were evaluated. Results show that EDAR can achieve higher throughput compared to other state of the art routing algorithms under various traffic patterns and levels of injected faults. In addition, the hardware area overhead for EDAR is demonstrated to have a reasonably low cost which maintains scalability for large NoC implementations. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1016/j.micpro.2015.06.002
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      – Code: eng
        Text: English
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        PageCount: 15
        StartPage: 358
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      – SubjectFull: Fault-tolerant computing
        Type: general
      – SubjectFull: Routing algorithms
        Type: general
      – SubjectFull: Networks on a chip
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      – SubjectFull: Adaptive computing systems
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            NameFull: Harkin, Jim
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            NameFull: Li, Yuhua
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              M: 08
              Text: Aug2015
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              Y: 2015
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