A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels.
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| Title: | A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. |
|---|---|
| Authors: | Zhu, Jianfeng1, Liu, Leibo1, Yin, Shouyi1, Yang, Xiao1, Wei, Shaojun1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Sep2015, Vol. 23 Issue 9, p1700-1709. 10p. |
| Subjects: | Parallel computers, Connection machines, Benchmark testing (Engineering), Multicore processors, Benchmark problems (Computer science) |
| Abstract: | With the development of parallel computing, the compute-intensive part of an application could be accelerated so dramatically that the control intensive part, usually processed by a sequential processor, is becoming more and more critical in terms of performance and power consumption. To address this problem, this paper proposes a novel reconfigurable architecture to execute control-intensive kernels efficiently. The architecture applies three key design methods. The first one, parallel condition, exploits the instruction level parallelism of conditional branches with hardware design. The second one, configuration branch, enables the architecture to independently execute an entire application that has loops and other control flows. The third one, compound configuration, combines multiple configurations of low hardware utilization, which are common in sequential codes particularly, and thus reduces the reconfiguring times. Therefore, to offload control-intensive kernels onto the proposed architecture will speed up these workloads and boost the overall performance. The experiments were conducted on a benchmark that contains various branches, loops, and sequential codes. The results showed that the proposed architecture alone could implement the benchmark correctly. In addition, the proposed methods can improve performance by over 40% compared with the conventional techniques. The power efficiency is two orders larger than general purpose processors. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 109065550 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Zhu%2C+Jianfeng%22">Zhu, Jianfeng</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Liu%2C+Leibo%22">Liu, Leibo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Yin%2C+Shouyi%22">Yin, Shouyi</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Yang%2C+Xiao%22">Yang, Xiao</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Wei%2C+Shaojun%22">Wei, Shaojun</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Sep2015, Vol. 23 Issue 9, p1700-1709. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Parallel+computers%22">Parallel computers</searchLink><br /><searchLink fieldCode="DE" term="%22Connection+machines%22">Connection machines</searchLink><br /><searchLink fieldCode="DE" term="%22Benchmark+testing+%28Engineering%29%22">Benchmark testing (Engineering)</searchLink><br /><searchLink fieldCode="DE" term="%22Multicore+processors%22">Multicore processors</searchLink><br /><searchLink fieldCode="DE" term="%22Benchmark+problems+%28Computer+science%29%22">Benchmark problems (Computer science)</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: With the development of parallel computing, the compute-intensive part of an application could be accelerated so dramatically that the control intensive part, usually processed by a sequential processor, is becoming more and more critical in terms of performance and power consumption. To address this problem, this paper proposes a novel reconfigurable architecture to execute control-intensive kernels efficiently. The architecture applies three key design methods. The first one, parallel condition, exploits the instruction level parallelism of conditional branches with hardware design. The second one, configuration branch, enables the architecture to independently execute an entire application that has loops and other control flows. The third one, compound configuration, combines multiple configurations of low hardware utilization, which are common in sequential codes particularly, and thus reduces the reconfiguring times. Therefore, to offload control-intensive kernels onto the proposed architecture will speed up these workloads and boost the overall performance. The experiments were conducted on a benchmark that contains various branches, loops, and sequential codes. The results showed that the proposed architecture alone could implement the benchmark correctly. In addition, the proposed methods can improve performance by over 40% compared with the conventional techniques. The power efficiency is two orders larger than general purpose processors. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2014.2349652 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 1700 Subjects: – SubjectFull: Parallel computers Type: general – SubjectFull: Connection machines Type: general – SubjectFull: Benchmark testing (Engineering) Type: general – SubjectFull: Multicore processors Type: general – SubjectFull: Benchmark problems (Computer science) Type: general Titles: – TitleFull: A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Zhu, Jianfeng – PersonEntity: Name: NameFull: Liu, Leibo – PersonEntity: Name: NameFull: Yin, Shouyi – PersonEntity: Name: NameFull: Yang, Xiao – PersonEntity: Name: NameFull: Wei, Shaojun IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep2015 Type: published Y: 2015 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 23 – Type: issue Value: 9 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
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