Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction.
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| Title: | Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction. |
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| Authors: | Junsangsri, Pilin1 junsangsri.p@husky.neu.edu, Han, Jie2 jhan8@ualberta.ca, Lombardi, Fabrizio1 lombardi@ece.neu.edu |
| Source: | Integration: The VLSI Journal. Jan2016, Vol. 52, p156-167. 12p. |
| Subjects: | Nonvolatile random-access memory, Concurrent error detection, Transistors, Computer storage devices, Hybrid power systems |
| Abstract: | This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6 T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit. [ABSTRACT FROM AUTHOR] |
| Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 111409424 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Junsangsri%2C+Pilin%22">Junsangsri, Pilin</searchLink><relatesTo>1</relatesTo><i> junsangsri.p@husky.neu.edu</i><br /><searchLink fieldCode="AR" term="%22Han%2C+Jie%22">Han, Jie</searchLink><relatesTo>2</relatesTo><i> jhan8@ualberta.ca</i><br /><searchLink fieldCode="AR" term="%22Lombardi%2C+Fabrizio%22">Lombardi, Fabrizio</searchLink><relatesTo>1</relatesTo><i> lombardi@ece.neu.edu</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Integration%3A+The+VLSI+Journal%22">Integration: The VLSI Journal</searchLink>. Jan2016, Vol. 52, p156-167. 12p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Nonvolatile+random-access+memory%22">Nonvolatile random-access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Concurrent+error+detection%22">Concurrent error detection</searchLink><br /><searchLink fieldCode="DE" term="%22Transistors%22">Transistors</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+storage+devices%22">Computer storage devices</searchLink><br /><searchLink fieldCode="DE" term="%22Hybrid+power+systems%22">Hybrid power systems</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6 T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=111409424 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.vlsi.2015.09.005 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 12 StartPage: 156 Subjects: – SubjectFull: Nonvolatile random-access memory Type: general – SubjectFull: Concurrent error detection Type: general – SubjectFull: Transistors Type: general – SubjectFull: Computer storage devices Type: general – SubjectFull: Hybrid power systems Type: general Titles: – TitleFull: Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Junsangsri, Pilin – PersonEntity: Name: NameFull: Han, Jie – PersonEntity: Name: NameFull: Lombardi, Fabrizio IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan2016 Type: published Y: 2016 Identifiers: – Type: issn-print Value: 01679260 Numbering: – Type: volume Value: 52 Titles: – TitleFull: Integration: The VLSI Journal Type: main |
| ResultId | 1 |
