Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction.
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| Title: | Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction. |
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| Authors: | Junsangsri, Pilin1 junsangsri.p@husky.neu.edu, Han, Jie2 jhan8@ualberta.ca, Lombardi, Fabrizio1 lombardi@ece.neu.edu |
| Source: | Integration: The VLSI Journal. Jan2016, Vol. 52, p156-167. 12p. |
| Subjects: | Nonvolatile random-access memory, Concurrent error detection, Transistors, Computer storage devices, Hybrid power systems |
| Abstract: | This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6 T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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