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Speculative Lookahead for Energy-Efficient Microprocessors.

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Title: Speculative Lookahead for Energy-Efficient Microprocessors.
Authors: Lin, Tay-Jyi1, Shyu, Ting-Yu1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2016, Vol. 24 Issue 1, p50-57. 8p.
Subjects: Microprocessor energy consumption, Power aware computing, CMOS integrated circuits, Fault-tolerant computing, Computer power supply management, Field programmable gate arrays
Abstract: In addition to being the in situ performance monitor for adaptive voltage scaling (AVS), timing speculation mechanisms (e.g., razor) featuring dynamic timing fault detection and correction help to relax timing constraints for simple logic structures and low-power cells. Conventional timing fault detection mechanisms require substantial buffers to prevent race conditions on short paths for double sampling, which can overwhelm energy savings from timing relaxation and voltage scaling. This paper proposes a novel timing speculation scheme, speculative lookahead (SL), comprising duplicate timing-relaxed datapaths, the short paths of which do not introduce race conditions and thus require no additional buffer insertion. In experiments using a 40-nm CMOS technology, SL consumed a 54.89% area of a razor-based 32-bit multiplier, and conserved 59.77% energy per operation at nominal 1.1 V and 53.49% when AVS was applied. An ARM Cortex M0-like microprocessor unit (MPU) was designed using an SL-based datapath, the timing fault detection and correction mechanism of which can be dynamically deactivated for latency-tolerant instructions [i.e., on-demand timing speculation (ODTS)] to further conserve up to 31.08% energy in the execution unit. In addition, an field-programmable gate array prototype of the SL/ODTS MPU was constructed to demonstrate the effectiveness of delay variation tolerance and implementation flexibility. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 111983279
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  Data: Speculative Lookahead for Energy-Efficient Microprocessors.
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  Data: <searchLink fieldCode="DE" term="%22Microprocessor+energy+consumption%22">Microprocessor energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Power+aware+computing%22">Power aware computing</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+integrated+circuits%22">CMOS integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Fault-tolerant+computing%22">Fault-tolerant computing</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+power+supply+management%22">Computer power supply management</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink>
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  Data: In addition to being the in situ performance monitor for adaptive voltage scaling (AVS), timing speculation mechanisms (e.g., razor) featuring dynamic timing fault detection and correction help to relax timing constraints for simple logic structures and low-power cells. Conventional timing fault detection mechanisms require substantial buffers to prevent race conditions on short paths for double sampling, which can overwhelm energy savings from timing relaxation and voltage scaling. This paper proposes a novel timing speculation scheme, speculative lookahead (SL), comprising duplicate timing-relaxed datapaths, the short paths of which do not introduce race conditions and thus require no additional buffer insertion. In experiments using a 40-nm CMOS technology, SL consumed a 54.89% area of a razor-based 32-bit multiplier, and conserved 59.77% energy per operation at nominal 1.1 V and 53.49% when AVS was applied. An ARM Cortex M0-like microprocessor unit (MPU) was designed using an SL-based datapath, the timing fault detection and correction mechanism of which can be dynamically deactivated for latency-tolerant instructions [i.e., on-demand timing speculation (ODTS)] to further conserve up to 31.08% energy in the execution unit. In addition, an field-programmable gate array prototype of the SL/ODTS MPU was constructed to demonstrate the effectiveness of delay variation tolerance and implementation flexibility. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TVLSI.2015.2397954
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        Text: English
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        Type: general
      – SubjectFull: Power aware computing
        Type: general
      – SubjectFull: CMOS integrated circuits
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      – SubjectFull: Fault-tolerant computing
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      – SubjectFull: Computer power supply management
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      – SubjectFull: Field programmable gate arrays
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              Text: Jan2016
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