Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead.
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| Title: | Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead. |
|---|---|
| Authors: | Liu, Junxiu1, Harkin, Jim1, Li, Yuhua2, Maguire, Liam P.1 |
| Source: | IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Feb2016, Vol. 35 Issue 2, p260-273. 14p. |
| Subjects: | Fault tolerance (Engineering), Integrated circuit design, Integrated circuits, Manufacturing processes, Routing (Computer network management) |
| Abstract: | Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC) due to the increase in physical defects in advanced manufacturing processes. Two novel adaptive routing algorithms, namely coarse and fine-grained (FG) look-ahead algorithms, are proposed in this paper to enhance 2-D mesh/torus NoC system fault-tolerant capabilities. These strategies use fault flag codes from neighboring nodes to obtain the status or conditions of real-time traffic in an NoC region, then calculate the path weights and choose the route to forward packets. This approach enables the router to minimize congestion for the adjacent connected channels and also to bypass a path with faulty channels by looking ahead at distant neighboring router paths. The novelty of the proposed routing algorithms is the weighted path selection strategies, which make near-optimal routing decisions to maintain the NoC system performance under high fault rates. Results show that the proposed routing algorithms can achieve performance improvement compared to other state of the art works under various traffic loads and high fault rates. The routing algorithm with FG look-ahead capability achieves a higher throughput compared with the coarse-grained approach under complex fault patterns. The hardware area/power overheads of both routing approaches are relatively low which does not prohibit scalability for large-scale NoC implementations. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 112441597 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Liu%2C+Junxiu%22">Liu, Junxiu</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Harkin%2C+Jim%22">Harkin, Jim</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Li%2C+Yuhua%22">Li, Yuhua</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Maguire%2C+Liam+P%2E%22">Maguire, Liam P.</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computer-Aided+Design+of+Integrated+Circuits+%26+Systems%22">IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems</searchLink>. Feb2016, Vol. 35 Issue 2, p260-273. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Fault+tolerance+%28Engineering%29%22">Fault tolerance (Engineering)</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+design%22">Integrated circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Manufacturing+processes%22">Manufacturing processes</searchLink><br /><searchLink fieldCode="DE" term="%22Routing+%28Computer+network+management%29%22">Routing (Computer network management)</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC) due to the increase in physical defects in advanced manufacturing processes. Two novel adaptive routing algorithms, namely coarse and fine-grained (FG) look-ahead algorithms, are proposed in this paper to enhance 2-D mesh/torus NoC system fault-tolerant capabilities. These strategies use fault flag codes from neighboring nodes to obtain the status or conditions of real-time traffic in an NoC region, then calculate the path weights and choose the route to forward packets. This approach enables the router to minimize congestion for the adjacent connected channels and also to bypass a path with faulty channels by looking ahead at distant neighboring router paths. The novelty of the proposed routing algorithms is the weighted path selection strategies, which make near-optimal routing decisions to maintain the NoC system performance under high fault rates. Results show that the proposed routing algorithms can achieve performance improvement compared to other state of the art works under various traffic loads and high fault rates. The routing algorithm with FG look-ahead capability achieves a higher throughput compared with the coarse-grained approach under complex fault patterns. The hardware area/power overheads of both routing approaches are relatively low which does not prohibit scalability for large-scale NoC implementations. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCAD.2015.2459050 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 260 Subjects: – SubjectFull: Fault tolerance (Engineering) Type: general – SubjectFull: Integrated circuit design Type: general – SubjectFull: Integrated circuits Type: general – SubjectFull: Manufacturing processes Type: general – SubjectFull: Routing (Computer network management) Type: general Titles: – TitleFull: Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Liu, Junxiu – PersonEntity: Name: NameFull: Harkin, Jim – PersonEntity: Name: NameFull: Li, Yuhua – PersonEntity: Name: NameFull: Maguire, Liam P. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 02 Text: Feb2016 Type: published Y: 2016 Identifiers: – Type: issn-print Value: 02780070 Numbering: – Type: volume Value: 35 – Type: issue Value: 2 Titles: – TitleFull: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems Type: main |
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