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Soft Core Processor Generated Based on the Machine Code of the Application.

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Title: Soft Core Processor Generated Based on the Machine Code of the Application.
Authors: Ziebinski, Adam1, Swierc, Stanwlaw1
Source: Journal of Circuits, Systems & Computers. Apr2016, Vol. 25 Issue 4, p1. 14p.
Subjects: Machine learning, Coding theory, Application software, Energy consumption, Computer input-output equipment
Abstract: Currently embedded system designs aim to improve areas such as speed, energy efficiency and the cost of an application. Application-specific instruction set extensions on reconfigurable hardware provide such opportunities. The article presents a new approach for generating soft core processors that are optimized for specific tasks. In this work, we describe an automatic method for selecting custom instructions for generating software core processors that are based on the machine code of the application program. As the result, a soft core processor will contain the logic that is absolutely necessary. This solution requires fewer gates to be synthesized in the field programmable gate arrays (FPGA) and has a potential to increase the speed of the information processing that is performed by the system in the target FPGA. Experiments have confirmed the correct operation of the method that was used. After the reduction mechanism was enabled, the total number of slices blocks that were occupied decreased to 47% of its initial value in the best case for the Xilinx Spartan3 (xc3s200) and the maximum frequency increased approximately 44% in the best case for Xilinx Spartan6 (xc6slx4). [ABSTRACT FROM AUTHOR]
Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Soft Core Processor Generated Based on the Machine Code of the Application.
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  Data: <searchLink fieldCode="AR" term="%22Ziebinski%2C+Adam%22">Ziebinski, Adam</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Swierc%2C+Stanwlaw%22">Swierc, Stanwlaw</searchLink><relatesTo>1</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22Journal+of+Circuits%2C+Systems+%26+Computers%22">Journal of Circuits, Systems & Computers</searchLink>. Apr2016, Vol. 25 Issue 4, p1. 14p.
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  Data: <searchLink fieldCode="DE" term="%22Machine+learning%22">Machine learning</searchLink><br /><searchLink fieldCode="DE" term="%22Coding+theory%22">Coding theory</searchLink><br /><searchLink fieldCode="DE" term="%22Application+software%22">Application software</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+input-output+equipment%22">Computer input-output equipment</searchLink>
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  Data: Currently embedded system designs aim to improve areas such as speed, energy efficiency and the cost of an application. Application-specific instruction set extensions on reconfigurable hardware provide such opportunities. The article presents a new approach for generating soft core processors that are optimized for specific tasks. In this work, we describe an automatic method for selecting custom instructions for generating software core processors that are based on the machine code of the application program. As the result, a soft core processor will contain the logic that is absolutely necessary. This solution requires fewer gates to be synthesized in the field programmable gate arrays (FPGA) and has a potential to increase the speed of the information processing that is performed by the system in the target FPGA. Experiments have confirmed the correct operation of the method that was used. After the reduction mechanism was enabled, the total number of slices blocks that were occupied decreased to 47% of its initial value in the best case for the Xilinx Spartan3 (xc3s200) and the maximum frequency increased approximately 44% in the best case for Xilinx Spartan6 (xc6slx4). [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
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  Data: <i>Copyright of Journal of Circuits, Systems & Computers is the property of World Scientific Publishing Company and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=112684856
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        Value: 10.1142/S0218126616500298
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      – Code: eng
        Text: English
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        PageCount: 14
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      – SubjectFull: Machine learning
        Type: general
      – SubjectFull: Coding theory
        Type: general
      – SubjectFull: Application software
        Type: general
      – SubjectFull: Energy consumption
        Type: general
      – SubjectFull: Computer input-output equipment
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      – TitleFull: Soft Core Processor Generated Based on the Machine Code of the Application.
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              Text: Apr2016
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              Y: 2016
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