APA (7th ed.) Citation

Jaewon Seo, N., Kim, T., & Panda, P. R. (2003). Memory Allocation and Mapping in High-Level Synthesis—An Integrated Approach. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(5), 928. https://doi.org/10.1109/TVLSI.2003.817116

Chicago Style (17th ed.) Citation

Jaewon Seo, Nagarajan, Taewhan Kim, and Preeti Ranjan Panda. "Memory Allocation and Mapping in High-Level Synthesis—An Integrated Approach." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, no. 5 (2003): 928. https://doi.org/10.1109/TVLSI.2003.817116.

MLA (9th ed.) Citation

Jaewon Seo, Nagarajan, et al. "Memory Allocation and Mapping in High-Level Synthesis—An Integrated Approach." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 5, 2003, p. 928, https://doi.org/10.1109/TVLSI.2003.817116.