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A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.

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Title: A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.
Authors: Kulkarni, Sarvesh H.1, Chen, Zhanping1, Srinivasan, Balaji2, Pedersen, Brian3, Bhattacharya, Uddalak1, Zhang, Kevin1
Source: IEEE Journal of Solid-State Circuits. Apr2016, Vol. 51 Issue 4, p1003-1008. 6p.
Subjects: Programmable read-only memory, CMOS integrated circuits, Integrated memory circuits, Programmable circuits, Integrated circuit design
Abstract: The first metal-fuse technology in 22 nm tri-gate high-k metal-gate CMOS technology is presented. The memory technology offerings in high-volume manufacturing include a 2.05\;\upmu \textm^2 2.2 V programmable high-density and a 16.4\,\upmu \textm^2 1.6 V programmable low-voltage (LV) 1T1R bit cell. The LV operability of the technology allows the fuse arrays to be coupled with power delivery circuits operating at standard logic voltage levels. A charge pump voltage doubler operating on a 1 V voltage rail is demonstrated in this paper with healthy fusing yield. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.
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  Data: <searchLink fieldCode="AR" term="%22Kulkarni%2C+Sarvesh+H%2E%22">Kulkarni, Sarvesh H.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Chen%2C+Zhanping%22">Chen, Zhanping</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Srinivasan%2C+Balaji%22">Srinivasan, Balaji</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Pedersen%2C+Brian%22">Pedersen, Brian</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Bhattacharya%2C+Uddalak%22">Bhattacharya, Uddalak</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Zhang%2C+Kevin%22">Zhang, Kevin</searchLink><relatesTo>1</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. Apr2016, Vol. 51 Issue 4, p1003-1008. 6p.
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  Data: <searchLink fieldCode="DE" term="%22Programmable+read-only+memory%22">Programmable read-only memory</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+integrated+circuits%22">CMOS integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+memory+circuits%22">Integrated memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Programmable+circuits%22">Programmable circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+design%22">Integrated circuit design</searchLink>
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  Data: The first metal-fuse technology in 22 nm tri-gate high-k metal-gate CMOS technology is presented. The memory technology offerings in high-volume manufacturing include a 2.05\;\upmu \textm^2 2.2 V programmable high-density and a 16.4\,\upmu \textm^2 1.6 V programmable low-voltage (LV) 1T1R bit cell. The LV operability of the technology allows the fuse arrays to be coupled with power delivery circuits operating at standard logic voltage levels. A charge pump voltage doubler operating on a 1 V voltage rail is demonstrated in this paper with healthy fusing yield. [ABSTRACT FROM PUBLISHER]
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  Label:
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  Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/JSSC.2015.2507786
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      – SubjectFull: CMOS integrated circuits
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      – SubjectFull: Integrated memory circuits
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