View in EDS PDF Full Text

Testability Synthesis for Jumping Carry Adders.

Saved in:
Bibliographic Details
Title: Testability Synthesis for Jumping Carry Adders.
Authors: Chen, Chien-in Henry1, Wagh, Mahesh1
Source: VLSI Design. Mar2002, Vol. 14 Issue 2, p155-169. 15p.
Subjects: Very large scale circuit integration, Methodology, Complementary metal oxide semiconductors, Electrical engineering
Abstract: Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy. With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit. The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed. This paper presents a testability synthesis methodology applicable to a top-down design method based on the identification and removal of redundant faults. Emphasis has been placed on the testability synthesis of a high-speed binary jumping carry adder. A synthesized 32-bit testable adder implemented by a 1.2 μm CMOS technology performs addition in 4.09 ns. Comparing with the original synthesized circuit, redundancy removal yields a 100% testable design with a 15% improvement in speed and a 25% reduction in area. [ABSTRACT FROM AUTHOR]
Copyright of VLSI Design is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
FullText Links:
  – Type: pdflink
Text:
  Availability: 0
Header DbId: egs
DbLabel: Engineering Source
An: 11557745
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: Testability Synthesis for Jumping Carry Adders.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Chen%2C+Chien-in+Henry%22">Chen, Chien-in Henry</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Wagh%2C+Mahesh%22">Wagh, Mahesh</searchLink><relatesTo>1</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22VLSI+Design%22">VLSI Design</searchLink>. Mar2002, Vol. 14 Issue 2, p155-169. 15p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Methodology%22">Methodology</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Electrical+engineering%22">Electrical engineering</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy. With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit. The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed. This paper presents a testability synthesis methodology applicable to a top-down design method based on the identification and removal of redundant faults. Emphasis has been placed on the testability synthesis of a high-speed binary jumping carry adder. A synthesized 32-bit testable adder implemented by a 1.2 μm CMOS technology performs addition in 4.09 ns. Comparing with the original synthesized circuit, redundancy removal yields a 100% testable design with a 15% improvement in speed and a 25% reduction in area. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of VLSI Design is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=11557745
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1080/10655140290010079
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 15
        StartPage: 155
    Subjects:
      – SubjectFull: Very large scale circuit integration
        Type: general
      – SubjectFull: Methodology
        Type: general
      – SubjectFull: Complementary metal oxide semiconductors
        Type: general
      – SubjectFull: Electrical engineering
        Type: general
    Titles:
      – TitleFull: Testability Synthesis for Jumping Carry Adders.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Chen, Chien-in Henry
      – PersonEntity:
          Name:
            NameFull: Wagh, Mahesh
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 03
              Text: Mar2002
              Type: published
              Y: 2002
          Identifiers:
            – Type: issn-print
              Value: 1065514X
          Numbering:
            – Type: volume
              Value: 14
            – Type: issue
              Value: 2
          Titles:
            – TitleFull: VLSI Design
              Type: main
ResultId 1