Timing-Driven-Testable Convergent Tree Adders.
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| Title: | Timing-Driven-Testable Convergent Tree Adders. |
|---|---|
| Authors: | Huang, Johnnie A.1, Chen, Chien-In Henry2 |
| Source: | VLSI Design. Nov2002, Vol. 15 Issue 3, p637-645. 9p. |
| Subjects: | Very large scale circuit integration, Integrated circuits, Integrated circuit interconnections, Cellular automata, Computer engineering |
| Abstract: | Carry lookahead adders have been, over the years, implemented in complex arithmetic units due to their regular structure which leads to efficient VLSI implementation for fast adders. In this paper, timing-driven testability synthesis is first performed on a tree adder. It is shown that the structure of the tree adder provides for a high fanout with an imbalanced tree structure, which likely contributes to a racing effect and increases the delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder, the optimization produces a 6.37% increase in speed of the critical path while only contributing a 2.16% area overhead. The full testability of the circuit is achieved in the optimized adder design. [ABSTRACT FROM AUTHOR] |
| Copyright of VLSI Design is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Timing-Driven-Testable Convergent Tree Adders. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Huang%2C+Johnnie+A%2E%22">Huang, Johnnie A.</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Chen%2C+Chien-In+Henry%22">Chen, Chien-In Henry</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22VLSI+Design%22">VLSI Design</searchLink>. Nov2002, Vol. 15 Issue 3, p637-645. 9p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+interconnections%22">Integrated circuit interconnections</searchLink><br /><searchLink fieldCode="DE" term="%22Cellular+automata%22">Cellular automata</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+engineering%22">Computer engineering</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Carry lookahead adders have been, over the years, implemented in complex arithmetic units due to their regular structure which leads to efficient VLSI implementation for fast adders. In this paper, timing-driven testability synthesis is first performed on a tree adder. It is shown that the structure of the tree adder provides for a high fanout with an imbalanced tree structure, which likely contributes to a racing effect and increases the delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder, the optimization produces a 6.37% increase in speed of the critical path while only contributing a 2.16% area overhead. The full testability of the circuit is achieved in the optimized adder design. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of VLSI Design is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1080/1065514021000012255 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 637 Subjects: – SubjectFull: Very large scale circuit integration Type: general – SubjectFull: Integrated circuits Type: general – SubjectFull: Integrated circuit interconnections Type: general – SubjectFull: Cellular automata Type: general – SubjectFull: Computer engineering Type: general Titles: – TitleFull: Timing-Driven-Testable Convergent Tree Adders. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Huang, Johnnie A. – PersonEntity: Name: NameFull: Chen, Chien-In Henry IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 11 Text: Nov2002 Type: published Y: 2002 Identifiers: – Type: issn-print Value: 1065514X Numbering: – Type: volume Value: 15 – Type: issue Value: 3 Titles: – TitleFull: VLSI Design Type: main |
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