Timing Challenges for Very Deep Sub-Micron (VDSM) IC.
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| Title: | Timing Challenges for Very Deep Sub-Micron (VDSM) IC. |
|---|---|
| Authors: | Ichiang Lin, Hannu1, Chen, Chien-In Henry2 |
| Source: | VLSI Design. Nov2002, Vol. 15 Issue 3, p557-562. 6p. |
| Subjects: | Integrated circuits, Integrated circuit interconnections, Very large scale circuit integration, Computer engineering |
| Abstract: | Many IC design houses failed to be market leaders because they miss the market window due to timing closure problems. Compared to half-micron designs, the amount of time spent on timing verification has greatly increased. Cell delays can be accurately estimated during logic synthesis. However, interconnect delays are unknown until the wire geometry is defined in physical design. Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately. Delay estimates for individual nets (global nets, long wires, large fan-outs, buses), which matter most for the critical paths can be inaccurate and cause a design failure. Inaccurate timing verification causes silicon failure in shipped products that results in the loss of millions of dollars spent designing a high-performance product and potentially larger costs due to lost market share. Full-chip, sign-off verification with silicon-accuracy will allow these problems to be discovered and fixed before tape-out. [ABSTRACT FROM AUTHOR] |
| Copyright of VLSI Design is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 11557789 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Timing Challenges for Very Deep Sub-Micron (VDSM) IC. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ichiang+Lin%2C+Hannu%22">Ichiang Lin, Hannu</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Chen%2C+Chien-In+Henry%22">Chen, Chien-In Henry</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22VLSI+Design%22">VLSI Design</searchLink>. Nov2002, Vol. 15 Issue 3, p557-562. 6p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+interconnections%22">Integrated circuit interconnections</searchLink><br /><searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+engineering%22">Computer engineering</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Many IC design houses failed to be market leaders because they miss the market window due to timing closure problems. Compared to half-micron designs, the amount of time spent on timing verification has greatly increased. Cell delays can be accurately estimated during logic synthesis. However, interconnect delays are unknown until the wire geometry is defined in physical design. Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately. Delay estimates for individual nets (global nets, long wires, large fan-outs, buses), which matter most for the critical paths can be inaccurate and cause a design failure. Inaccurate timing verification causes silicon failure in shipped products that results in the loss of millions of dollars spent designing a high-performance product and potentially larger costs due to lost market share. Full-chip, sign-off verification with silicon-accuracy will allow these problems to be discovered and fixed before tape-out. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of VLSI Design is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1080/1065514021000012183 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 6 StartPage: 557 Subjects: – SubjectFull: Integrated circuits Type: general – SubjectFull: Integrated circuit interconnections Type: general – SubjectFull: Very large scale circuit integration Type: general – SubjectFull: Computer engineering Type: general Titles: – TitleFull: Timing Challenges for Very Deep Sub-Micron (VDSM) IC. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ichiang Lin, Hannu – PersonEntity: Name: NameFull: Chen, Chien-In Henry IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 11 Text: Nov2002 Type: published Y: 2002 Identifiers: – Type: issn-print Value: 1065514X Numbering: – Type: volume Value: 15 – Type: issue Value: 3 Titles: – TitleFull: VLSI Design Type: main |
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