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On hardware synthesis and implementation of PLC programs in FPGAs.

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Title: On hardware synthesis and implementation of PLC programs in FPGAs.
Authors: Milik, Adam1 adam.milik@polsl.pl
Source: Microprocessors & Microsystems. Jul2016, Vol. 44, p2-16. 15p.
Subjects: Programmable logic devices, Hardware, Numerical control of machine tools, Automation, Digital mapping, Microprocessors
Abstract: Many processes require controllers with an instant response (e.g. motor control, CNC machines). A high-performance PLC can be constructed with use of programmable logic devices. A lack of custom synthesis tools disables the use of standard languages widely accepted by automation designers. The paper presents the systematic process of a PLC program synthesis to hardware structure. An input PLC program is given according to the IEC61131-3 standard. The synthesis process has been developed for implementation of a program described with the LD and SFC languages. The essential idea of synthesis process is obtaining a massively parallel operating hardware structure that significantly reduces response processing time. The PLC program is translated into originally developed dedicated graph structure that enables a wide range of optimizations. In the next step, it is mapped into a hardware structure. In order to reduce resource requirements, a strategy with resource sharing is shown, which is an original extension of general mapping concepts. Modern FPGAs are equipped with arithmetic cores dedicated for signal processing, inspiring the development of the original DSP48 block mapping strategy. It attempts to utilize all features of the block in the pipelined calculation model. The considerations are summarized with the implementation result compared against standard PLC implementation, a mutual comparison of general hardware mapping, and with the use of DSP48 units. [ABSTRACT FROM AUTHOR]
Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
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PubType: Academic Journal
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  Data: On hardware synthesis and implementation of PLC programs in FPGAs.
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  Data: <searchLink fieldCode="AR" term="%22Milik%2C+Adam%22">Milik, Adam</searchLink><relatesTo>1</relatesTo><i> adam.milik@polsl.pl</i>
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  Data: <searchLink fieldCode="JN" term="%22Microprocessors+%26+Microsystems%22">Microprocessors & Microsystems</searchLink>. Jul2016, Vol. 44, p2-16. 15p.
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  Data: <searchLink fieldCode="DE" term="%22Programmable+logic+devices%22">Programmable logic devices</searchLink><br /><searchLink fieldCode="DE" term="%22Hardware%22">Hardware</searchLink><br /><searchLink fieldCode="DE" term="%22Numerical+control+of+machine+tools%22">Numerical control of machine tools</searchLink><br /><searchLink fieldCode="DE" term="%22Automation%22">Automation</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+mapping%22">Digital mapping</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink>
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  Label: Abstract
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  Data: Many processes require controllers with an instant response (e.g. motor control, CNC machines). A high-performance PLC can be constructed with use of programmable logic devices. A lack of custom synthesis tools disables the use of standard languages widely accepted by automation designers. The paper presents the systematic process of a PLC program synthesis to hardware structure. An input PLC program is given according to the IEC61131-3 standard. The synthesis process has been developed for implementation of a program described with the LD and SFC languages. The essential idea of synthesis process is obtaining a massively parallel operating hardware structure that significantly reduces response processing time. The PLC program is translated into originally developed dedicated graph structure that enables a wide range of optimizations. In the next step, it is mapped into a hardware structure. In order to reduce resource requirements, a strategy with resource sharing is shown, which is an original extension of general mapping concepts. Modern FPGAs are equipped with arithmetic cores dedicated for signal processing, inspiring the development of the original DSP48 block mapping strategy. It attempts to utilize all features of the block in the pipelined calculation model. The considerations are summarized with the implementation result compared against standard PLC implementation, a mutual comparison of general hardware mapping, and with the use of DSP48 units. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1016/j.micpro.2016.02.003
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      – Code: eng
        Text: English
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        PageCount: 15
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      – SubjectFull: Programmable logic devices
        Type: general
      – SubjectFull: Hardware
        Type: general
      – SubjectFull: Numerical control of machine tools
        Type: general
      – SubjectFull: Automation
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      – SubjectFull: Digital mapping
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      – TitleFull: On hardware synthesis and implementation of PLC programs in FPGAs.
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              Text: Jul2016
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              Y: 2016
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