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A $4\times 5$ -Gb/s 1.12- \mu \text{s} Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels.

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Title: A $4\times 5$ -Gb/s 1.12- \mu \text{s} Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels.
Authors: Song, Junyoung1, Hwang, Sewook1, Kim, Chulwoo1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Aug2016, Vol. 24 Issue 8, p2768-2777. 10p.
Subjects: CMOS memory circuits, Clock & data recovery circuits, Bandwidths, MOS memory circuits, Integrated memory circuits
Abstract: A 4\times 5 -Gb/s reference-less receiver is proposed in a 0.13- \mu \text{m} CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12- \mu \text{s}$ locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 {\rm ps}_{{\mathrm{rms}}} , and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively. [ABSTRACT FROM PUBLISHER]
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Database: Engineering Source
Description
Abstract:A 4\times 5 -Gb/s reference-less receiver is proposed in a 0.13- \mu \text{m} CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12- \mu \text{s}$ locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 {\rm ps}_{{\mathrm{rms}}} , and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively. [ABSTRACT FROM PUBLISHER]
ISSN:10638210
DOI:10.1109/TVLSI.2016.2520584