A $4\times 5$ -Gb/s 1.12- \mu \text{s} Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels.
Saved in:
| Title: | A $4\times 5$ -Gb/s 1.12- \mu \text{s} Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. |
|---|---|
| Authors: | Song, Junyoung1, Hwang, Sewook1, Kim, Chulwoo1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Aug2016, Vol. 24 Issue 8, p2768-2777. 10p. |
| Subjects: | CMOS memory circuits, Clock & data recovery circuits, Bandwidths, MOS memory circuits, Integrated memory circuits |
| Abstract: | A 4\times 5 -Gb/s reference-less receiver is proposed in a 0.13- \mu \text{m} CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12- \mu \text{s}$ locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 {\rm ps}_{{\mathrm{rms}}} , and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
|---|---|
| Header | DbId: egs DbLabel: Engineering Source An: 117001810 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: A $4\times 5$ -Gb/s 1.12- \mu \text{s} Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Song%2C+Junyoung%22">Song, Junyoung</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Hwang%2C+Sewook%22">Hwang, Sewook</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kim%2C+Chulwoo%22">Kim, Chulwoo</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Aug2016, Vol. 24 Issue 8, p2768-2777. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22CMOS+memory+circuits%22">CMOS memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Clock+%26+data+recovery+circuits%22">Clock & data recovery circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Bandwidths%22">Bandwidths</searchLink><br /><searchLink fieldCode="DE" term="%22MOS+memory+circuits%22">MOS memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+memory+circuits%22">Integrated memory circuits</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: A 4\times 5 -Gb/s reference-less receiver is proposed in a 0.13- \mu \text{m} CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12- \mu \text{s}$ locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 {\rm ps}_{{\mathrm{rms}}} , and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=117001810 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2016.2520584 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 2768 Subjects: – SubjectFull: CMOS memory circuits Type: general – SubjectFull: Clock & data recovery circuits Type: general – SubjectFull: Bandwidths Type: general – SubjectFull: MOS memory circuits Type: general – SubjectFull: Integrated memory circuits Type: general Titles: – TitleFull: A $4\times 5$ -Gb/s 1.12- \mu \text{s} Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Song, Junyoung – PersonEntity: Name: NameFull: Hwang, Sewook – PersonEntity: Name: NameFull: Kim, Chulwoo IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 08 Text: Aug2016 Type: published Y: 2016 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 24 – Type: issue Value: 8 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
| ResultId | 1 |
