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Memory write speed up via multi voltage driver on CeidMem Library.

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Title: Memory write speed up via multi voltage driver on CeidMem Library.
Authors: Simopoulos, T.1 simopoulos@ceid.upatras.gr, Haniotakis, T.2, Alexiou, G.Ph.1
Source: Microelectronic Engineering. Sep2016, Vol. 163, p21-25. 5p.
Subjects: Electric potential, Random access memory, Permittivity, Electric resistors, Electric circuits, Microelectronics
Abstract: A speedup technique for the write function of static memories, achieved via multi voltage manipulation, is presented. The designs created to support this technique and the test circuit that verifies the percentage of the speedup are implemented on physical layout level using the Ceid's CeidMem Static Memory Library and the Ceid's Standard Cell Library. Throughout this technique, the memory write procedure is driven by different voltage levels having as target the write permittivity of each memory cell on the same row to be triggered by an edge pulse on the memory word line signal. This way the memory only triggers the writing procedure, enabling rapid consecutive writes on different rows. The simulation of the test circuit is done in analog level using the extracted view of the cells which are integrated with their parasitic resistors and capacitors. Taking into account the parasitic resistors and capacitors of the test circuit as a whole, the test results are at the most accurate. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:A speedup technique for the write function of static memories, achieved via multi voltage manipulation, is presented. The designs created to support this technique and the test circuit that verifies the percentage of the speedup are implemented on physical layout level using the Ceid's CeidMem Static Memory Library and the Ceid's Standard Cell Library. Throughout this technique, the memory write procedure is driven by different voltage levels having as target the write permittivity of each memory cell on the same row to be triggered by an edge pulse on the memory word line signal. This way the memory only triggers the writing procedure, enabling rapid consecutive writes on different rows. The simulation of the test circuit is done in analog level using the extracted view of the cells which are integrated with their parasitic resistors and capacitors. Taking into account the parasitic resistors and capacitors of the test circuit as a whole, the test results are at the most accurate. [ABSTRACT FROM AUTHOR]
ISSN:01679317
DOI:10.1016/j.mee.2016.05.018