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A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads.

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Title: A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads.
Authors: Zarate-Roldan, Jorge1, Wang, Mengde2, Torres, Joselyn2, Sanchez-Sinencio, Edgar1
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Sep2016, Vol. 24 Issue 9, p2970-2982. 13p.
Subjects: Systems on a chip, On-chip charge pumps, Static random access memory chips, Electric capacity, CMOS integrated circuits, Voltage regulators
Abstract: This paper presents an on-chip, low drop-out (LDO) voltage regulator with improved power-supply rejection (PSR) able to drive large capacitive loads. The LDO compensation is achieved via a custom, wide bandwidth capacitance multiplier (c-multiplier) that emulates a nanofarad-range capacitance at the LDO output node. The LDO frequency response resembles that of externally compensated LDOs, leading to a wide PSR frequency range without using an off-chip capacitor. To drive large capacitive loads without stability concerns, the supply-line capacitance of the load circuit is incorporated to the design of the LDO compensation scheme. The power-stability-performance tradeoffs involved in the design are discussed in detail. The LDO and the c-multiplier are implemented in 0.18- \mu \textm CMOS technology and target applications with load currents in the 10-mA range. Experimental results show that the LDO achieves a PSR better than −39 dB up to 20 MHz at 1.2 V output voltage, while maintaining a 97.4% current efficiency. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
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  Data: A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads.
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  Data: <searchLink fieldCode="DE" term="%22Systems+on+a+chip%22">Systems on a chip</searchLink><br /><searchLink fieldCode="DE" term="%22On-chip+charge+pumps%22">On-chip charge pumps</searchLink><br /><searchLink fieldCode="DE" term="%22Static+random+access+memory+chips%22">Static random access memory chips</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+capacity%22">Electric capacity</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+integrated+circuits%22">CMOS integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Voltage+regulators%22">Voltage regulators</searchLink>
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  Data: This paper presents an on-chip, low drop-out (LDO) voltage regulator with improved power-supply rejection (PSR) able to drive large capacitive loads. The LDO compensation is achieved via a custom, wide bandwidth capacitance multiplier (c-multiplier) that emulates a nanofarad-range capacitance at the LDO output node. The LDO frequency response resembles that of externally compensated LDOs, leading to a wide PSR frequency range without using an off-chip capacitor. To drive large capacitive loads without stability concerns, the supply-line capacitance of the load circuit is incorporated to the design of the LDO compensation scheme. The power-stability-performance tradeoffs involved in the design are discussed in detail. The LDO and the c-multiplier are implemented in 0.18- \mu \textm CMOS technology and target applications with load currents in the 10-mA range. Experimental results show that the LDO achieves a PSR better than −39 dB up to 20 MHz at 1.2 V output voltage, while maintaining a 97.4% current efficiency. [ABSTRACT FROM PUBLISHER]
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  Label:
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  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TVLSI.2016.2527681
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      – Code: eng
        Text: English
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        Type: general
      – SubjectFull: On-chip charge pumps
        Type: general
      – SubjectFull: Static random access memory chips
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      – SubjectFull: Electric capacity
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      – SubjectFull: CMOS integrated circuits
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      – SubjectFull: Voltage regulators
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      – TitleFull: A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads.
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            NameFull: Wang, Mengde
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              Text: Sep2016
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