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Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures.

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Title: Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures.
Authors: Zhang, Weihua1, Yu, Shiqiang1, Wang, Haojun1, Dai, Zhuofang1, Chen, Haibo2
Source: IEEE Transactions on Computers. Oct2016, Vol. 65 Issue 10, p3083-3095. 13p.
Subjects: Computer input-output equipment, Concurrent error detection, Central processing units, Graphics processing units, Computer architecture, Data analysis
Abstract: Detecting concurrency bugs, such as data race, atomicity violation and order violation, is a cumbersome task for programmers. This situation is further being exacerbated due to the increasing number of cores in a single machine and the prevalence of threaded programming models. Unfortunately, many existing software-based approaches usually incur high runtime overhead or accuracy loss, while most hardware-based proposals usually focus on a specific type of bugs and thus are inflexible to detect a variety of concurrency bugs. In this paper, we propose Hydra, an approach that leverages massive parallelism and programmability of fused CPU-GPU architectures to simultaneously detect multiple concurrency bugs in threaded software, including data race, atomicity violation and order violation. Hydra extends contemporary fused CPU and GPU by introducing two modules: 1) a trace collecting module (TCM) that instruments and collects program behavior on CPU; 2) a trace preprocessing module (TPM) that processes and then transfers the traces to GPU for bug detection. Furthermore, Hydra exploits three optimizations to improve speed and accuracy, which includes: 1). using the bloom filter to filter out unnecessary traces; 2). avoiding eviction of shared traces; 3). comparing only last-write traces for shared data with the happens-before relation. Hydra incurs small hardware complexity and requires no changes to internal critical-path processor components such as cache and its coherence protocol, and is with about 1.1 percent hardware overhead under a 32-core configuration. Experimental results show that Hydra only introduces about 0.18 percent overhead on average for detecting one type of bugs and 0.46 percent overhead for simultaneously detecting multiple bugs, yet with the similar detectability of a heavyweight software bug detector (e.g., Helgrind). [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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Header DbId: egs
DbLabel: Engineering Source
An: 118004538
AccessLevel: 6
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PubTypeId: academicJournal
PreciseRelevancyScore: 0
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Zhang%2C+Weihua%22">Zhang, Weihua</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Yu%2C+Shiqiang%22">Yu, Shiqiang</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Wang%2C+Haojun%22">Wang, Haojun</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Dai%2C+Zhuofang%22">Dai, Zhuofang</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Chen%2C+Haibo%22">Chen, Haibo</searchLink><relatesTo>2</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computers%22">IEEE Transactions on Computers</searchLink>. Oct2016, Vol. 65 Issue 10, p3083-3095. 13p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Computer+input-output+equipment%22">Computer input-output equipment</searchLink><br /><searchLink fieldCode="DE" term="%22Concurrent+error+detection%22">Concurrent error detection</searchLink><br /><searchLink fieldCode="DE" term="%22Central+processing+units%22">Central processing units</searchLink><br /><searchLink fieldCode="DE" term="%22Graphics+processing+units%22">Graphics processing units</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Data+analysis%22">Data analysis</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Detecting concurrency bugs, such as data race, atomicity violation and order violation, is a cumbersome task for programmers. This situation is further being exacerbated due to the increasing number of cores in a single machine and the prevalence of threaded programming models. Unfortunately, many existing software-based approaches usually incur high runtime overhead or accuracy loss, while most hardware-based proposals usually focus on a specific type of bugs and thus are inflexible to detect a variety of concurrency bugs. In this paper, we propose Hydra, an approach that leverages massive parallelism and programmability of fused CPU-GPU architectures to simultaneously detect multiple concurrency bugs in threaded software, including data race, atomicity violation and order violation. Hydra extends contemporary fused CPU and GPU by introducing two modules: 1) a trace collecting module (TCM) that instruments and collects program behavior on CPU; 2) a trace preprocessing module (TPM) that processes and then transfers the traces to GPU for bug detection. Furthermore, Hydra exploits three optimizations to improve speed and accuracy, which includes: 1). using the bloom filter to filter out unnecessary traces; 2). avoiding eviction of shared traces; 3). comparing only last-write traces for shared data with the happens-before relation. Hydra incurs small hardware complexity and requires no changes to internal critical-path processor components such as cache and its coherence protocol, and is with about 1.1 percent hardware overhead under a 32-core configuration. Experimental results show that Hydra only introduces about 0.18 percent overhead on average for detecting one type of bugs and 0.46 percent overhead for simultaneously detecting multiple bugs, yet with the similar detectability of a heavyweight software bug detector (e.g., Helgrind). [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1109/TC.2015.2512860
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 13
        StartPage: 3083
    Subjects:
      – SubjectFull: Computer input-output equipment
        Type: general
      – SubjectFull: Concurrent error detection
        Type: general
      – SubjectFull: Central processing units
        Type: general
      – SubjectFull: Graphics processing units
        Type: general
      – SubjectFull: Computer architecture
        Type: general
      – SubjectFull: Data analysis
        Type: general
    Titles:
      – TitleFull: Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Zhang, Weihua
      – PersonEntity:
          Name:
            NameFull: Yu, Shiqiang
      – PersonEntity:
          Name:
            NameFull: Wang, Haojun
      – PersonEntity:
          Name:
            NameFull: Dai, Zhuofang
      – PersonEntity:
          Name:
            NameFull: Chen, Haibo
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 10
              Text: Oct2016
              Type: published
              Y: 2016
          Identifiers:
            – Type: issn-print
              Value: 00189340
          Numbering:
            – Type: volume
              Value: 65
            – Type: issue
              Value: 10
          Titles:
            – TitleFull: IEEE Transactions on Computers
              Type: main
ResultId 1