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RAMS: DRAM Rank-Aware Memory Scheduling for Energy Saving.

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Bibliographic Details
Title: RAMS: DRAM Rank-Aware Memory Scheduling for Energy Saving.
Authors: Lee, Yebin1, Kim, Soontae1
Source: IEEE Transactions on Computers. Oct2016, Vol. 65 Issue 10, p3210-3216. 7p.
Subjects: Random access memory, Dynamic random access memory, Computer scheduling, Computer storage devices, Energy consumption
Abstract: DRAMs are one of the main players of the computer system energy consumption. Thus, reducing DRAM energy consumption has a big potential to save the entire system energy consumption. Because the standby power consumption of DRAM is significant, modern DRAMs provide low-power modes for reducing idle energy consumption. However, the use of low-power modes can degrade the performance because state transitions to/from low-power states involve a time penalty. To effectively utilize low-power modes, we propose DRAM rank-aware memory scheduling schemes. One scheme utilizes a prioritized cache block replacement method considering the power states of DRAM ranks to select victim blocks for the late level cache. Through this scheme, DRAM traffic and the number of state transitions of DRAM ranks can be reduced. The other scheme utilizes the memory controller by controlling write traffic to DRAM with the awareness of the DRAM rank states. DRAM rank idle times and state transitions can be reduced by this scheme. Our proposed schemes are shown to reduce DRAM energy consumption by 15.2 percent on average. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:DRAMs are one of the main players of the computer system energy consumption. Thus, reducing DRAM energy consumption has a big potential to save the entire system energy consumption. Because the standby power consumption of DRAM is significant, modern DRAMs provide low-power modes for reducing idle energy consumption. However, the use of low-power modes can degrade the performance because state transitions to/from low-power states involve a time penalty. To effectively utilize low-power modes, we propose DRAM rank-aware memory scheduling schemes. One scheme utilizes a prioritized cache block replacement method considering the power states of DRAM ranks to select victim blocks for the late level cache. Through this scheme, DRAM traffic and the number of state transitions of DRAM ranks can be reduced. The other scheme utilizes the memory controller by controlling write traffic to DRAM with the awareness of the DRAM rank states. DRAM rank idle times and state transitions can be reduced by this scheme. Our proposed schemes are shown to reduce DRAM energy consumption by 15.2 percent on average. [ABSTRACT FROM AUTHOR]
ISSN:00189340
DOI:10.1109/TC.2016.2525994