APA (7th ed.) Citation

Sitik, C., Liu, W., Taskin, B., & Salman, E. (2016). Design Methodology for Voltage-Scaled Clock Distribution Networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(10), 3080. https://doi.org/10.1109/TVLSI.2016.2539926

Chicago Style (17th ed.) Citation

Sitik, Can, Weicheng Liu, Baris Taskin, and Emre Salman. "Design Methodology for Voltage-Scaled Clock Distribution Networks." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 10 (2016): 3080. https://doi.org/10.1109/TVLSI.2016.2539926.

MLA (9th ed.) Citation

Sitik, Can, et al. "Design Methodology for Voltage-Scaled Clock Distribution Networks." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 10, 2016, p. 3080, https://doi.org/10.1109/TVLSI.2016.2539926.