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Design Methodology for Voltage-Scaled Clock Distribution Networks.

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Title: Design Methodology for Voltage-Scaled Clock Distribution Networks.
Authors: Sitik, Can1, Liu, Weicheng2, Taskin, Baris1, Salman, Emre2
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Oct2016, Vol. 24 Issue 10, p3080-3093. 14p.
Subjects: Clock distribution networks, Electric circuit networks, Clock circuits (Electronics), Energy consumption, Energy conservation
Abstract: A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: 1) a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the entire clock network and 2) a novel clock tree synthesis algorithm to ensure that the same timing constraints (i.e., clock frequency, skew, and slew) are satisfied. The proposed methodology is integrated within an industrial design flow. Experimental results on ISCAS’89 benchmark circuits demonstrate that the overall power consumed by the clock tree can be reduced by up to 27% and 44% in, respectively, 32- and 45-nm technologies while satisfying the same timing constraints. Furthermore, the proposed low-swing DFF cell maintains the clock-to-Q delay the same while achieving up to 32% and 15% power savings in the overall flip-flop power of the benchmark circuits at, respectively, 1- and 1.5-GHz clock frequencies. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 118364323
AccessLevel: 6
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PubTypeId: academicJournal
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: Design Methodology for Voltage-Scaled Clock Distribution Networks.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Sitik%2C+Can%22">Sitik, Can</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Liu%2C+Weicheng%22">Liu, Weicheng</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Taskin%2C+Baris%22">Taskin, Baris</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Salman%2C+Emre%22">Salman, Emre</searchLink><relatesTo>2</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Oct2016, Vol. 24 Issue 10, p3080-3093. 14p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Clock+distribution+networks%22">Clock distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+circuit+networks%22">Electric circuit networks</searchLink><br /><searchLink fieldCode="DE" term="%22Clock+circuits+%28Electronics%29%22">Clock circuits (Electronics)</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+conservation%22">Energy conservation</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: 1) a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the entire clock network and 2) a novel clock tree synthesis algorithm to ensure that the same timing constraints (i.e., clock frequency, skew, and slew) are satisfied. The proposed methodology is integrated within an industrial design flow. Experimental results on ISCAS’89 benchmark circuits demonstrate that the overall power consumed by the clock tree can be reduced by up to 27% and 44% in, respectively, 32- and 45-nm technologies while satisfying the same timing constraints. Furthermore, the proposed low-swing DFF cell maintains the clock-to-Q delay the same while achieving up to 32% and 15% power savings in the overall flip-flop power of the benchmark circuits at, respectively, 1- and 1.5-GHz clock frequencies. [ABSTRACT FROM PUBLISHER]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1109/TVLSI.2016.2539926
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 14
        StartPage: 3080
    Subjects:
      – SubjectFull: Clock distribution networks
        Type: general
      – SubjectFull: Electric circuit networks
        Type: general
      – SubjectFull: Clock circuits (Electronics)
        Type: general
      – SubjectFull: Energy consumption
        Type: general
      – SubjectFull: Energy conservation
        Type: general
    Titles:
      – TitleFull: Design Methodology for Voltage-Scaled Clock Distribution Networks.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Sitik, Can
      – PersonEntity:
          Name:
            NameFull: Liu, Weicheng
      – PersonEntity:
          Name:
            NameFull: Taskin, Baris
      – PersonEntity:
          Name:
            NameFull: Salman, Emre
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 10
              Text: Oct2016
              Type: published
              Y: 2016
          Identifiers:
            – Type: issn-print
              Value: 10638210
          Numbering:
            – Type: volume
              Value: 24
            – Type: issue
              Value: 10
          Titles:
            – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
              Type: main
ResultId 1