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Improving Resource Utilization by Curbing Speculative Trace Progression in Simultaneous Multi-Threading CPUs.

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Title: Improving Resource Utilization by Curbing Speculative Trace Progression in Simultaneous Multi-Threading CPUs.
Authors: YILIN ZHANG1 zhangyilin.bupt@gmail.com, WEI-MING LIN2 weiming.lin@utsa.edu
Source: Journal of Information Science & Engineering. Nov2016, Vol. 32 Issue 6, p1487-1502. 16p.
Subjects: Resource management, Simultaneous multithreading processors, Central processing units, Queuing theory, Control theory (Engineering)
Abstract: Simultaneous Multi-Threading (SMT) improves the overall performance of superscalar CPUs by allowing concurrent execution of multiple independent threads with sharing of key datapath components in order to better utilize the resources. Speculative executions help modern processors to exploit more Instruction-Level Parallelism. However, the performance penalty from a miss speculation is much more prominent in an SMT environment than a traditional multi-threading system due to the resulted waste of shared resources at clock-cycle level, versus thread level. In this paper, we show that instructions fetched due to incorrect prediction can be more than 30% of all instructions, which results in a huge waste of resources that could have been better used by other non-speculative threads. To minimize this waste of resources, a technique is proposed in this paper to control the amount of speculative instructions dispatched into Issue Queue (IQ), the most critically shared resource in the SMT pipeline. Simulation result shows the proposed technique can reduce the waste of resource due to miss-speculated traces by 38% and improve overall throughput by up to 17% in IPC. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Information Science & Engineering is the property of Institute of Information Science, Academia Sinica and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: <searchLink fieldCode="DE" term="%22Resource+management%22">Resource management</searchLink><br /><searchLink fieldCode="DE" term="%22Simultaneous+multithreading+processors%22">Simultaneous multithreading processors</searchLink><br /><searchLink fieldCode="DE" term="%22Central+processing+units%22">Central processing units</searchLink><br /><searchLink fieldCode="DE" term="%22Queuing+theory%22">Queuing theory</searchLink><br /><searchLink fieldCode="DE" term="%22Control+theory+%28Engineering%29%22">Control theory (Engineering)</searchLink>
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  Data: Simultaneous Multi-Threading (SMT) improves the overall performance of superscalar CPUs by allowing concurrent execution of multiple independent threads with sharing of key datapath components in order to better utilize the resources. Speculative executions help modern processors to exploit more Instruction-Level Parallelism. However, the performance penalty from a miss speculation is much more prominent in an SMT environment than a traditional multi-threading system due to the resulted waste of shared resources at clock-cycle level, versus thread level. In this paper, we show that instructions fetched due to incorrect prediction can be more than 30% of all instructions, which results in a huge waste of resources that could have been better used by other non-speculative threads. To minimize this waste of resources, a technique is proposed in this paper to control the amount of speculative instructions dispatched into Issue Queue (IQ), the most critically shared resource in the SMT pipeline. Simulation result shows the proposed technique can reduce the waste of resource due to miss-speculated traces by 38% and improve overall throughput by up to 17% in IPC. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
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  Data: <i>Copyright of Journal of Information Science & Engineering is the property of Institute of Information Science, Academia Sinica and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Text: English
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        PageCount: 16
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      – SubjectFull: Resource management
        Type: general
      – SubjectFull: Simultaneous multithreading processors
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      – SubjectFull: Central processing units
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      – SubjectFull: Queuing theory
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      – SubjectFull: Control theory (Engineering)
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      – TitleFull: Improving Resource Utilization by Curbing Speculative Trace Progression in Simultaneous Multi-Threading CPUs.
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              Text: Nov2016
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