Melia: A MapReduce Framework on OpenCL-Based FPGAs.
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| Title: | Melia: A MapReduce Framework on OpenCL-Based FPGAs. |
|---|---|
| Authors: | Wang, Zeke1, Zhang, Shuhao1, He, Bingsheng1, Zhang, Wei2 |
| Source: | IEEE Transactions on Parallel & Distributed Systems. Dec2016, Vol. 27 Issue 12, p3547-3560. 14p. |
| Subjects: | Software architecture, Computer software development -- Environmental aspects, Field programmable gate arrays, Computer programming, Electronic data processing |
| Abstract: | MapReduce, originally developed by Google for search applications, has recently become a popular programming framework for parallel and distributed environments. This paper presents an energy-efficient architecture design for MapReduce on Field Programmable Gate Arrays (FPGAs). The major goal is to enable users to program FPGAs with simple MapReduce interfaces, and meanwhile to embrace automatic performance optimizations within the MapReduce framework. Compared to other processors like CPUs and GPUs, FPGAs are (re-)programmable hardware and have very low energy consumption. However, the design and implementation of MapReduce on FPGAs can be challenging: firstly, FPGAs are usually programmed with hardware description languages, which hurts the programmability of the MapReduce design to its users; secondly, since MapReduce has irregular access patterns (especially in the reduce phase) and needs to support user-defined functions, careful designs and optimizations are required for efficiency. In this paper, we design, implement and evaluate Melia, a MapReduce framework on FPGAs. Melia takes advantage of the recent OpenCL programming framework developed for Altera FPGAs, and abstracts FPGAs behind the simple and familiar MapReduce interfaces in C. We further develop a series of FPGA-centric optimization techniques to improve the efficiency of Melia, and a cost- and resource-based approach to automate the parameter settings for those optimizations. We evaluate Melia on a recent Altera Stratix V GX FPGA with a number of commonly used MapReduce benchmarks. Our results demonstrate that 1) the efficiency and effectiveness of our optimizations and automated parameter setting approach, 2) Melia can achieve promising energy efficiency in comparison with its counterparts on CPUs/GPUs on both single-FPGA and cluster settings. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Parallel & Distributed Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 119492209 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Melia: A MapReduce Framework on OpenCL-Based FPGAs. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Wang%2C+Zeke%22">Wang, Zeke</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Zhang%2C+Shuhao%22">Zhang, Shuhao</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22He%2C+Bingsheng%22">He, Bingsheng</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Zhang%2C+Wei%22">Zhang, Wei</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Parallel+%26+Distributed+Systems%22">IEEE Transactions on Parallel & Distributed Systems</searchLink>. Dec2016, Vol. 27 Issue 12, p3547-3560. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Software+architecture%22">Software architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+software+development+--+Environmental+aspects%22">Computer software development -- Environmental aspects</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+programming%22">Computer programming</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+data+processing%22">Electronic data processing</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: MapReduce, originally developed by Google for search applications, has recently become a popular programming framework for parallel and distributed environments. This paper presents an energy-efficient architecture design for MapReduce on Field Programmable Gate Arrays (FPGAs). The major goal is to enable users to program FPGAs with simple MapReduce interfaces, and meanwhile to embrace automatic performance optimizations within the MapReduce framework. Compared to other processors like CPUs and GPUs, FPGAs are (re-)programmable hardware and have very low energy consumption. However, the design and implementation of MapReduce on FPGAs can be challenging: firstly, FPGAs are usually programmed with hardware description languages, which hurts the programmability of the MapReduce design to its users; secondly, since MapReduce has irregular access patterns (especially in the reduce phase) and needs to support user-defined functions, careful designs and optimizations are required for efficiency. In this paper, we design, implement and evaluate Melia, a MapReduce framework on FPGAs. Melia takes advantage of the recent OpenCL programming framework developed for Altera FPGAs, and abstracts FPGAs behind the simple and familiar MapReduce interfaces in C. We further develop a series of FPGA-centric optimization techniques to improve the efficiency of Melia, and a cost- and resource-based approach to automate the parameter settings for those optimizations. We evaluate Melia on a recent Altera Stratix V GX FPGA with a number of commonly used MapReduce benchmarks. Our results demonstrate that 1) the efficiency and effectiveness of our optimizations and automated parameter setting approach, 2) Melia can achieve promising energy efficiency in comparison with its counterparts on CPUs/GPUs on both single-FPGA and cluster settings. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Parallel & Distributed Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TPDS.2016.2537805 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 3547 Subjects: – SubjectFull: Software architecture Type: general – SubjectFull: Computer software development -- Environmental aspects Type: general – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Computer programming Type: general – SubjectFull: Electronic data processing Type: general Titles: – TitleFull: Melia: A MapReduce Framework on OpenCL-Based FPGAs. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Wang, Zeke – PersonEntity: Name: NameFull: Zhang, Shuhao – PersonEntity: Name: NameFull: He, Bingsheng – PersonEntity: Name: NameFull: Zhang, Wei IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: Dec2016 Type: published Y: 2016 Identifiers: – Type: issn-print Value: 10459219 Numbering: – Type: volume Value: 27 – Type: issue Value: 12 Titles: – TitleFull: IEEE Transactions on Parallel & Distributed Systems Type: main |
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