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Scalable Networks-on-Chip Interconnected Architecture for Astrocyte-Neuron Networks.

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Title: Scalable Networks-on-Chip Interconnected Architecture for Astrocyte-Neuron Networks.
Authors: Liu, Junxiu1, Harkin, Jim1, Maguire, Liam P.1, McDaid, Liam J.1, Wade, John J.1, Martin, George1
Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Dec2016, Vol. 63 Issue 12, p2290-2303. 14p.
Subjects: Astrocytes, Neurons, Mammals, Electronic circuits, Hardware, International communication, Scalability
Abstract: Spiking astrocyte-neuron networks (ANNs) have the potential to emulate the self-repair capability in the mammalian brain. Recent research has explored the mimicking of this capability in hardware with the aim to make electronic circuits autonomous with self-detection and repair. The provision of hardware architectures and interconnectivity between the massive numbers of spiking neurons and astrocytes is a significant research challenge, as the neuron and astrocyte networks have different communication patterns. In particular they have large volumes of information exchanges. This paper presents a novel interconnected architecture for ANN hardware systems based on the hierarchical astrocyte network architecture (HANA). HANA supports the information exchanges between astrocyte cells and addresses the interconnection challenge by providing a novel hierarchical networks-on-chip (NoC) structure of neurons and astrocytes cells. The proposed HANA incorporates a priority scheduling mechanism to increase the information exchange rate for global astrocyte cells, thus reducing the global communication latency and providing a balance between the local and global astrocyte network traffic. Experimental results demonstrate that the proposed HANA architecture can provide efficient information exchange rates for ANN, while the hardware synthesis results demonstrates that it has a low area utilization and power consumption which supports scalability. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
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PubType: Periodical
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  Data: Scalable Networks-on-Chip Interconnected Architecture for Astrocyte-Neuron Networks.
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  Data: <searchLink fieldCode="DE" term="%22Astrocytes%22">Astrocytes</searchLink><br /><searchLink fieldCode="DE" term="%22Neurons%22">Neurons</searchLink><br /><searchLink fieldCode="DE" term="%22Mammals%22">Mammals</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+circuits%22">Electronic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Hardware%22">Hardware</searchLink><br /><searchLink fieldCode="DE" term="%22International+communication%22">International communication</searchLink><br /><searchLink fieldCode="DE" term="%22Scalability%22">Scalability</searchLink>
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  Data: Spiking astrocyte-neuron networks (ANNs) have the potential to emulate the self-repair capability in the mammalian brain. Recent research has explored the mimicking of this capability in hardware with the aim to make electronic circuits autonomous with self-detection and repair. The provision of hardware architectures and interconnectivity between the massive numbers of spiking neurons and astrocytes is a significant research challenge, as the neuron and astrocyte networks have different communication patterns. In particular they have large volumes of information exchanges. This paper presents a novel interconnected architecture for ANN hardware systems based on the hierarchical astrocyte network architecture (HANA). HANA supports the information exchanges between astrocyte cells and addresses the interconnection challenge by providing a novel hierarchical networks-on-chip (NoC) structure of neurons and astrocytes cells. The proposed HANA incorporates a priority scheduling mechanism to increase the information exchange rate for global astrocyte cells, thus reducing the global communication latency and providing a balance between the local and global astrocyte network traffic. Experimental results demonstrate that the proposed HANA architecture can provide efficient information exchange rates for ANN, while the hardware synthesis results demonstrates that it has a low area utilization and power consumption which supports scalability. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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        Value: 10.1109/TCSI.2016.2615051
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      – SubjectFull: Astrocytes
        Type: general
      – SubjectFull: Neurons
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      – SubjectFull: Mammals
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              Text: Dec2016
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