Frequency-Translational Quadrature-Hybrid Receivers for Very-Low-Noise, Frequency-Agile, Scalable Inter-Band Carrier Aggregation.
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| Title: | Frequency-Translational Quadrature-Hybrid Receivers for Very-Low-Noise, Frequency-Agile, Scalable Inter-Band Carrier Aggregation. |
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| Authors: | Zhu, Jianxun1, Kinget, Peter R.1 |
| Source: | IEEE Journal of Solid-State Circuits. Dec2016, Vol. 51 Issue 12, p3137-3151. 15p. |
| Subjects: | CMOS memory circuits, Quadrature amplitude modulation |
| Abstract: | A frequency-translational quadrature-hybrid receiver is proposed that achieves wideband input matching for a reflective low-noise-amplifier input impedance and enables the realization of wideband, concurrent receivers. Frequency-agile, inter-band carrier aggregation is realized from a single antenna through RF signal sharing and quadrature-hybrid-coupler daisy chaining. A 1.1 V 65 nm CMOS prototype chip is demonstrated that has a sub-1 dB minimum NF, a 12 MHz to 70 MHz RF bandwidth, a +8 dBm IIP3 , and a −15 dBm B1dB and consumes <58 mW per channel. The prototypes have been integrated into a demonstration system that features 4-band inter-band carrier aggregation with modulated carriers placed between 0.69 and 2.1 GHz and received with an EVM <2.8%. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 120010707 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Frequency-Translational Quadrature-Hybrid Receivers for Very-Low-Noise, Frequency-Agile, Scalable Inter-Band Carrier Aggregation. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Zhu%2C+Jianxun%22">Zhu, Jianxun</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kinget%2C+Peter+R%2E%22">Kinget, Peter R.</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Journal+of+Solid-State+Circuits%22">IEEE Journal of Solid-State Circuits</searchLink>. Dec2016, Vol. 51 Issue 12, p3137-3151. 15p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22CMOS+memory+circuits%22">CMOS memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Quadrature+amplitude+modulation%22">Quadrature amplitude modulation</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: A frequency-translational quadrature-hybrid receiver is proposed that achieves wideband input matching for a reflective low-noise-amplifier input impedance and enables the realization of wideband, concurrent receivers. Frequency-agile, inter-band carrier aggregation is realized from a single antenna through RF signal sharing and quadrature-hybrid-coupler daisy chaining. A 1.1 V 65 nm CMOS prototype chip is demonstrated that has a sub-1 dB minimum NF, a 12 MHz to 70 MHz RF bandwidth, a +8 dBm IIP3 , and a −15 dBm B1dB and consumes <58 mW per channel. The prototypes have been integrated into a demonstration system that features 4-band inter-band carrier aggregation with modulated carriers placed between 0.69 and 2.1 GHz and received with an EVM <2.8%. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/JSSC.2016.2597154 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 15 StartPage: 3137 Subjects: – SubjectFull: CMOS memory circuits Type: general – SubjectFull: Quadrature amplitude modulation Type: general Titles: – TitleFull: Frequency-Translational Quadrature-Hybrid Receivers for Very-Low-Noise, Frequency-Agile, Scalable Inter-Band Carrier Aggregation. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Zhu, Jianxun – PersonEntity: Name: NameFull: Kinget, Peter R. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: Dec2016 Type: published Y: 2016 Identifiers: – Type: issn-print Value: 00189200 Numbering: – Type: volume Value: 51 – Type: issue Value: 12 Titles: – TitleFull: IEEE Journal of Solid-State Circuits Type: main |
| ResultId | 1 |
