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Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations.

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Title: Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations.
Authors: Gomez, A.F.1 fgomez@inaoep.mx, Lavratti, F.2, Medeiros, G.2, Sartori, M.2, Poehls, L. Bolzani2 leticia@poehls.com, Champac, V.1 champac@inaoep.mx, Vargas, F.2
Source: Microelectronics Reliability. Dec2016, Vol. 67, p150-158. 9p.
Subjects: Static random access memory, Integrated memory circuits, Electric testing, Integrated circuits, Phase change memory
Abstract: Resistive-open defects in Static Random Access Memories (SRAMs) represent an important challenge for manufacturing test in submicron technologies as they may be masked by process variations, which in turn increases the number of test escapes. This paper evaluates the effectiveness of a hardware-based test approach that compares the current consumption of neighboring SRAM cells to detect resistive-open defects. The proposed approach is validated and its fault detection capabilities are analyzed for different defect sizes and taking into account process variations effects. Finally, the paper provides an evaluation of the minimum detectable resistive-open defect size for the proposed hardware-based approach under process variations effects. [ABSTRACT FROM AUTHOR]
Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 120147281
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PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations.
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  Data: <searchLink fieldCode="AR" term="%22Gomez%2C+A%2EF%2E%22">Gomez, A.F.</searchLink><relatesTo>1</relatesTo><i> fgomez@inaoep.mx</i><br /><searchLink fieldCode="AR" term="%22Lavratti%2C+F%2E%22">Lavratti, F.</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Medeiros%2C+G%2E%22">Medeiros, G.</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Sartori%2C+M%2E%22">Sartori, M.</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Poehls%2C+L%2E+Bolzani%22">Poehls, L. Bolzani</searchLink><relatesTo>2</relatesTo><i> leticia@poehls.com</i><br /><searchLink fieldCode="AR" term="%22Champac%2C+V%2E%22">Champac, V.</searchLink><relatesTo>1</relatesTo><i> champac@inaoep.mx</i><br /><searchLink fieldCode="AR" term="%22Vargas%2C+F%2E%22">Vargas, F.</searchLink><relatesTo>2</relatesTo>
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  Data: <searchLink fieldCode="JN" term="%22Microelectronics+Reliability%22">Microelectronics Reliability</searchLink>. Dec2016, Vol. 67, p150-158. 9p.
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  Data: <searchLink fieldCode="DE" term="%22Static+random+access+memory%22">Static random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+memory+circuits%22">Integrated memory circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+testing%22">Electric testing</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Phase+change+memory%22">Phase change memory</searchLink>
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  Data: Resistive-open defects in Static Random Access Memories (SRAMs) represent an important challenge for manufacturing test in submicron technologies as they may be masked by process variations, which in turn increases the number of test escapes. This paper evaluates the effectiveness of a hardware-based test approach that compares the current consumption of neighboring SRAM cells to detect resistive-open defects. The proposed approach is validated and its fault detection capabilities are analyzed for different defect sizes and taking into account process variations effects. Finally, the paper provides an evaluation of the minimum detectable resistive-open defect size for the proposed hardware-based approach under process variations effects. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
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  Data: <i>Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1016/j.microrel.2016.10.012
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