The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology.
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| Title: | The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology. |
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| Authors: | Halak, Basel1, Tenentes, Vasileios1 V.Tenentes@ecs.soton.ac.uk, Rossi, Daniele2 D.Rossi@westminster.ac.uk |
| Source: | Microelectronics Reliability. Dec2016, Vol. 67, p74-81. 8p. |
| Subjects: | Integrated circuit design, Semiconductor wafer bonding, CMOS logic circuits, Integrated circuit layout, Complementary metal oxide semiconductors |
| Abstract: | On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are much more robust to BTI aging degradation. To the best of our knowledge, this is the first work addressing the effects of BTI on the the delay and power consumption of level shifters. [ABSTRACT FROM AUTHOR] |
| Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 120147301 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Halak%2C+Basel%22">Halak, Basel</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Tenentes%2C+Vasileios%22">Tenentes, Vasileios</searchLink><relatesTo>1</relatesTo><i> V.Tenentes@ecs.soton.ac.uk</i><br /><searchLink fieldCode="AR" term="%22Rossi%2C+Daniele%22">Rossi, Daniele</searchLink><relatesTo>2</relatesTo><i> D.Rossi@westminster.ac.uk</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Microelectronics+Reliability%22">Microelectronics Reliability</searchLink>. Dec2016, Vol. 67, p74-81. 8p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Integrated+circuit+design%22">Integrated circuit design</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductor+wafer+bonding%22">Semiconductor wafer bonding</searchLink><br /><searchLink fieldCode="DE" term="%22CMOS+logic+circuits%22">CMOS logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuit+layout%22">Integrated circuit layout</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are much more robust to BTI aging degradation. To the best of our knowledge, this is the first work addressing the effects of BTI on the the delay and power consumption of level shifters. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Microelectronics Reliability is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.microrel.2016.10.018 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 8 StartPage: 74 Subjects: – SubjectFull: Integrated circuit design Type: general – SubjectFull: Semiconductor wafer bonding Type: general – SubjectFull: CMOS logic circuits Type: general – SubjectFull: Integrated circuit layout Type: general – SubjectFull: Complementary metal oxide semiconductors Type: general Titles: – TitleFull: The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Halak, Basel – PersonEntity: Name: NameFull: Tenentes, Vasileios – PersonEntity: Name: NameFull: Rossi, Daniele IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 12 Text: Dec2016 Type: published Y: 2016 Identifiers: – Type: issn-print Value: 00262714 Numbering: – Type: volume Value: 67 Titles: – TitleFull: Microelectronics Reliability Type: main |
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