Fast clock scheduling and an application to clock tree synthesis.
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| Title: | Fast clock scheduling and an application to clock tree synthesis. |
|---|---|
| Authors: | Ewetz, Rickard1 rewetz@purdue.edu, Koh, Cheng-Kok1 chengkok@purdue.edu |
| Source: | Integration: The VLSI Journal. Jan2017, Vol. 56, p115-127. 13p. |
| Subjects: | Clock distribution networks, Low voltage integrated circuits, Topology, Electrical engineering, Robust control, Computer science |
| Abstract: | Clock networks are required to be constructed with adequate safety margins in the skew constraints to operate correctly even under the influence of variations. In this work, a scalable clock scheduler is developed to drive a synthesis framework that constructs useful skew clock trees with large safety margins that are tailored to the tree topology. Sequential elements are clustered early in the topology, if it is impossible provide adequate robustness to variations using only safety margins. Compared to earlier studies, the proposed framework performs the clock scheduling one to two orders of magnitude faster and improves yield and capacitive cost on several synthesized circuits. [ABSTRACT FROM AUTHOR] |
| Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 120295445 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Fast clock scheduling and an application to clock tree synthesis. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Ewetz%2C+Rickard%22">Ewetz, Rickard</searchLink><relatesTo>1</relatesTo><i> rewetz@purdue.edu</i><br /><searchLink fieldCode="AR" term="%22Koh%2C+Cheng-Kok%22">Koh, Cheng-Kok</searchLink><relatesTo>1</relatesTo><i> chengkok@purdue.edu</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Integration%3A+The+VLSI+Journal%22">Integration: The VLSI Journal</searchLink>. Jan2017, Vol. 56, p115-127. 13p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Clock+distribution+networks%22">Clock distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Low+voltage+integrated+circuits%22">Low voltage integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Topology%22">Topology</searchLink><br /><searchLink fieldCode="DE" term="%22Electrical+engineering%22">Electrical engineering</searchLink><br /><searchLink fieldCode="DE" term="%22Robust+control%22">Robust control</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+science%22">Computer science</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Clock networks are required to be constructed with adequate safety margins in the skew constraints to operate correctly even under the influence of variations. In this work, a scalable clock scheduler is developed to drive a synthesis framework that constructs useful skew clock trees with large safety margins that are tailored to the tree topology. Sequential elements are clustered early in the topology, if it is impossible provide adequate robustness to variations using only safety margins. Compared to earlier studies, the proposed framework performs the clock scheduling one to two orders of magnitude faster and improves yield and capacitive cost on several synthesized circuits. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=120295445 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.vlsi.2016.10.012 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 115 Subjects: – SubjectFull: Clock distribution networks Type: general – SubjectFull: Low voltage integrated circuits Type: general – SubjectFull: Topology Type: general – SubjectFull: Electrical engineering Type: general – SubjectFull: Robust control Type: general – SubjectFull: Computer science Type: general Titles: – TitleFull: Fast clock scheduling and an application to clock tree synthesis. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Ewetz, Rickard – PersonEntity: Name: NameFull: Koh, Cheng-Kok IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 01679260 Numbering: – Type: volume Value: 56 Titles: – TitleFull: Integration: The VLSI Journal Type: main |
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