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Boundary optimization of buffered clock trees for low power.

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Bibliographic Details
Title: Boundary optimization of buffered clock trees for low power.
Authors: Kim, Joohan1, Kim, Taewhan1
Source: Integration: The VLSI Journal. Jan2017, Vol. 56, p86-95. 10p.
Subjects: Clock distribution networks, Energy consumption, Mathematical optimization, Flip-flop circuits, Automation, Algorithms
Abstract: The work solves a new problem of optimizing the boundary of buffered clock trees, which has not been addressed in the design automation as yet. Precisely, we want to show that the clock cells that directly drive flip-flops should not necessarily be buffers. By taking into account the internal structure of flip-flops, we can have a freedom of choosing either buffers or inverters for the cell implementation from library. This in fact leads to cancel out the two inverters, one in the driving buffer and another in each flip-flop, thereby reducing the power consumption on the clock tree, including flip-flops. We generalize this idea to look into the possibility of co-optimizing the driving buffers and flip-flops together to reduce the clock power at the boundary of clock trees, and propose an effective four-step synthesis algorithm of clock tree boundary for low power. By applying our proposed technique to benchmark circuits, it is observed that the clock power is able to be reduced by 4.45 % ∼ 6.33 % further on average without timing violation. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:The work solves a new problem of optimizing the boundary of buffered clock trees, which has not been addressed in the design automation as yet. Precisely, we want to show that the clock cells that directly drive flip-flops should not necessarily be buffers. By taking into account the internal structure of flip-flops, we can have a freedom of choosing either buffers or inverters for the cell implementation from library. This in fact leads to cancel out the two inverters, one in the driving buffer and another in each flip-flop, thereby reducing the power consumption on the clock tree, including flip-flops. We generalize this idea to look into the possibility of co-optimizing the driving buffers and flip-flops together to reduce the clock power at the boundary of clock trees, and propose an effective four-step synthesis algorithm of clock tree boundary for low power. By applying our proposed technique to benchmark circuits, it is observed that the clock power is able to be reduced by 4.45 % ∼ 6.33 % further on average without timing violation. [ABSTRACT FROM AUTHOR]
ISSN:01679260
DOI:10.1016/j.vlsi.2016.10.004