New structures of the concurrent error detection systems for logic circuits.
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| Title: | New structures of the concurrent error detection systems for logic circuits. |
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| Authors: | Sapozhnikov, V.1 port.at.pgups@gmail.com, Sapozhnikov, Vl.1 at.pgups@gmail.com, Efanov, D.1 TrES-4b@yandex.ru, Dmitriev, V.1 d2c.tool@gmail.com |
| Source: | Automation & Remote Control. Feb2017, Vol. 78 Issue 2, p300-312. 13p. |
| Subjects: | Concurrent error detection, Logic circuits, Mathematical sequences, Mathematical analysis, Electronic information resources |
| Abstract: | Proposed were new structures for concurrent error detection systems of the combinatorial logic circuits based on the codes with summation of the weighted transitions and their modifications. They were compared with the traditional systems of duplication and check by the Berger code. The structure based on the code with summation of the weighted transitions allowed one to improve the index of realization complexity as compared with the duplication system by 4 % on the average. The structure obtained by modifying the code with summation of the weighted transitions into the optimal code enables one to improve this index almost twice as much as compared with the system of checking by the Berger code. At that, this system has a better index of error detection. In certain cases, the structure of the concurrent error detection system on the basis of the optimal code is superior in complexity to the system of parity check. [ABSTRACT FROM AUTHOR] |
| Copyright of Automation & Remote Control is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 121237834 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1134/S0005117917020096 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 300 Subjects: – SubjectFull: Concurrent error detection Type: general – SubjectFull: Logic circuits Type: general – SubjectFull: Mathematical sequences Type: general – SubjectFull: Mathematical analysis Type: general – SubjectFull: Electronic information resources Type: general Titles: – TitleFull: New structures of the concurrent error detection systems for logic circuits. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Sapozhnikov, V. – PersonEntity: Name: NameFull: Sapozhnikov, Vl. – PersonEntity: Name: NameFull: Efanov, D. – PersonEntity: Name: NameFull: Dmitriev, V. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 02 Text: Feb2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 00051179 Numbering: – Type: volume Value: 78 – Type: issue Value: 2 Titles: – TitleFull: Automation & Remote Control Type: main |
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