APA (7th ed.) Citation

Joo, D., & Kim, T. (2017). Clock buffer polarity assignment under useful skew constraints. Integration: The VLSI Journal, 57, 52. https://doi.org/10.1016/j.vlsi.2016.11.007

Chicago Style (17th ed.) Citation

Joo, Deokjin, and Taewhan Kim. "Clock Buffer Polarity Assignment Under Useful Skew Constraints." Integration: The VLSI Journal 57 (2017): 52. https://doi.org/10.1016/j.vlsi.2016.11.007.

MLA (9th ed.) Citation

Joo, Deokjin, and Taewhan Kim. "Clock Buffer Polarity Assignment Under Useful Skew Constraints." Integration: The VLSI Journal, vol. 57, 2017, p. 52, https://doi.org/10.1016/j.vlsi.2016.11.007.