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Clock buffer polarity assignment under useful skew constraints.

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Title: Clock buffer polarity assignment under useful skew constraints.
Authors: Joo, Deokjin1, Kim, Taewhan1 tkim@ssl.snu.ac.kr
Source: Integration: The VLSI Journal. Mar2017, Vol. 57, p52-61. 10p.
Subjects: Clock distribution networks, Signal processing, Scalability, Algorithms, Problem solving
Abstract: Clock trees, which deliver the clock signal to every clock sink in the whole system, switch actively at high frequency, which makes them one of the most dominant sources of noise. While many clock polarity assignment (PA) techniques were proposed to mitigate the clock noise, no attention has been paid to the PA under useful skew constraints. In this work, we show that the clock PA problem under useful skew constraints is intractable and propose a comprehensive and scalable clique search based algorithm to solve the problem effectively. In addition, we demonstrate the applicability of our solution by extending it for PA under delay variation environment. Through experiments with ISPD'10 benchmark circuits, we show that our proposed clock PA algorithm is able to reduce the peak noise by 10.9% further over that of the conventional global skew bound constrained PA. Finally, we compare our PA technique against decoupling capacitor embedding technique which is a commonly used method for noise reduction. [ABSTRACT FROM AUTHOR]
Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Header DbId: egs
DbLabel: Engineering Source
An: 121356605
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
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  Data: Clock buffer polarity assignment under useful skew constraints.
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  Data: <searchLink fieldCode="AR" term="%22Joo%2C+Deokjin%22">Joo, Deokjin</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kim%2C+Taewhan%22">Kim, Taewhan</searchLink><relatesTo>1</relatesTo><i> tkim@ssl.snu.ac.kr</i>
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  Data: <searchLink fieldCode="JN" term="%22Integration%3A+The+VLSI+Journal%22">Integration: The VLSI Journal</searchLink>. Mar2017, Vol. 57, p52-61. 10p.
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  Data: <searchLink fieldCode="DE" term="%22Clock+distribution+networks%22">Clock distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Signal+processing%22">Signal processing</searchLink><br /><searchLink fieldCode="DE" term="%22Scalability%22">Scalability</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Problem+solving%22">Problem solving</searchLink>
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  Label: Abstract
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  Data: Clock trees, which deliver the clock signal to every clock sink in the whole system, switch actively at high frequency, which makes them one of the most dominant sources of noise. While many clock polarity assignment (PA) techniques were proposed to mitigate the clock noise, no attention has been paid to the PA under useful skew constraints. In this work, we show that the clock PA problem under useful skew constraints is intractable and propose a comprehensive and scalable clique search based algorithm to solve the problem effectively. In addition, we demonstrate the applicability of our solution by extending it for PA under delay variation environment. Through experiments with ISPD'10 benchmark circuits, we show that our proposed clock PA algorithm is able to reduce the peak noise by 10.9% further over that of the conventional global skew bound constrained PA. Finally, we compare our PA technique against decoupling capacitor embedding technique which is a commonly used method for noise reduction. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1016/j.vlsi.2016.11.007
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      – Code: eng
        Text: English
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        PageCount: 10
        StartPage: 52
    Subjects:
      – SubjectFull: Clock distribution networks
        Type: general
      – SubjectFull: Signal processing
        Type: general
      – SubjectFull: Scalability
        Type: general
      – SubjectFull: Algorithms
        Type: general
      – SubjectFull: Problem solving
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      – TitleFull: Clock buffer polarity assignment under useful skew constraints.
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            NameFull: Joo, Deokjin
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              Text: Mar2017
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              Y: 2017
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              Value: 57
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            – TitleFull: Integration: The VLSI Journal
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