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An approach for analyzing auto-vectorization potential of emerging workloads.

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Title: An approach for analyzing auto-vectorization potential of emerging workloads.
Authors: Yazdanpanah, Fahimeh1 fahim_yazdan@yahoo.com
Source: Microprocessors & Microsystems. Mar2017, Vol. 49, p139-149. 11p.
Subjects: Parsec, SIMD (Computer architecture), Loops (Group theory), Workload of computer networks, Compilers (Computer programs)
Abstract: This paper presents an analytical study on PARSEC benchmark suite in order to examine the auto-vectorization potential of emerging workloads by ICC and GCC compilers. For investigating auto-vectorization potential, we have analyzed the amount of vectorized and non-vectorized loops and the number of vector instructions of application. We have found most of the time-consuming loops of the applications have not been vectorized. Then, we have modified the applications and profiled them again. We have shown applying the modifications have a considerable effect on the amount of vectorized loops but the number of instructions has not reduced to what we expect because of the limited size of SIMD-width of current processors. As a result, in addition to applying some algorithmic methods such as loop unrolling, splitting large loops, definition of data structures, replacing function calls in loops with function bodies removing control flows from the loops in possible cases and so on to help the compilers for auto-vectorization, increasing the SIMD-width of the vector extension of CPUs is an important issue in order to improve the speed and performance. [ABSTRACT FROM AUTHOR]
Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 121357034
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
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  Data: An approach for analyzing auto-vectorization potential of emerging workloads.
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  Data: <searchLink fieldCode="JN" term="%22Microprocessors+%26+Microsystems%22">Microprocessors & Microsystems</searchLink>. Mar2017, Vol. 49, p139-149. 11p.
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  Data: <searchLink fieldCode="DE" term="%22Parsec%22">Parsec</searchLink><br /><searchLink fieldCode="DE" term="%22SIMD+%28Computer+architecture%29%22">SIMD (Computer architecture)</searchLink><br /><searchLink fieldCode="DE" term="%22Loops+%28Group+theory%29%22">Loops (Group theory)</searchLink><br /><searchLink fieldCode="DE" term="%22Workload+of+computer+networks%22">Workload of computer networks</searchLink><br /><searchLink fieldCode="DE" term="%22Compilers+%28Computer+programs%29%22">Compilers (Computer programs)</searchLink>
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  Data: This paper presents an analytical study on PARSEC benchmark suite in order to examine the auto-vectorization potential of emerging workloads by ICC and GCC compilers. For investigating auto-vectorization potential, we have analyzed the amount of vectorized and non-vectorized loops and the number of vector instructions of application. We have found most of the time-consuming loops of the applications have not been vectorized. Then, we have modified the applications and profiled them again. We have shown applying the modifications have a considerable effect on the amount of vectorized loops but the number of instructions has not reduced to what we expect because of the limited size of SIMD-width of current processors. As a result, in addition to applying some algorithmic methods such as loop unrolling, splitting large loops, definition of data structures, replacing function calls in loops with function bodies removing control flows from the loops in possible cases and so on to help the compilers for auto-vectorization, increasing the SIMD-width of the vector extension of CPUs is an important issue in order to improve the speed and performance. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Microprocessors & Microsystems is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1016/j.micpro.2016.11.014
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      – Code: eng
        Text: English
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      Pagination:
        PageCount: 11
        StartPage: 139
    Subjects:
      – SubjectFull: Parsec
        Type: general
      – SubjectFull: SIMD (Computer architecture)
        Type: general
      – SubjectFull: Loops (Group theory)
        Type: general
      – SubjectFull: Workload of computer networks
        Type: general
      – SubjectFull: Compilers (Computer programs)
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      – TitleFull: An approach for analyzing auto-vectorization potential of emerging workloads.
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              Text: Mar2017
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              Value: 49
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