CMCS: Current-Mode Clock Synthesis.
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| Title: | CMCS: Current-Mode Clock Synthesis. |
|---|---|
| Authors: | Islam, Riadul1, Guthaus, Matthew R.1 |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Mar2017, Vol. 25 Issue 3, p1054-1062. 9p. |
| Subjects: | Clock distribution networks, Current-mode circuits, Low voltage integrated circuits |
| Abstract: | In a high-performance VLSI design, the clock network consumes a significant amount of power. While most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous amount of dynamic power to charge/discharge the large global clock capacitance. New circuit approaches for current-mode (CM) clocking save significant clock power, but have been limited to only symmetric networks, while most application specific integrated circuits have asymmetric clock distributions. In this paper, we propose the first CM clock synthesis (CMCS) methodology to reduce the overall clock network power with low skew. The method can integrate with traditional clock routing followed by transmitter and receiver sizing. We validate the proposed methodology using ISPD 2009 and 2010 industrial benchmarks using an extracted SPICE model distributed in 1.4–275.6-mm2 area and consists of 81–2249 sinks. This methodology saves 39%–84% average power with similar skew on the benchmarks using 45-nm CMOS technology simulation of clock frequencies range from 1–3 GHz. In addition, the CMCS methodology takes $2.4-9.1\times $ less running time and consumes 20%–26% less transistor area compared with synthesized, buffered VM clock distributions. [ABSTRACT FROM PUBLISHER] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 121461729 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: CMCS: Current-Mode Clock Synthesis. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Islam%2C+Riadul%22">Islam, Riadul</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Guthaus%2C+Matthew+R%2E%22">Guthaus, Matthew R.</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Mar2017, Vol. 25 Issue 3, p1054-1062. 9p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Clock+distribution+networks%22">Clock distribution networks</searchLink><br /><searchLink fieldCode="DE" term="%22Current-mode+circuits%22">Current-mode circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Low+voltage+integrated+circuits%22">Low voltage integrated circuits</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In a high-performance VLSI design, the clock network consumes a significant amount of power. While most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous amount of dynamic power to charge/discharge the large global clock capacitance. New circuit approaches for current-mode (CM) clocking save significant clock power, but have been limited to only symmetric networks, while most application specific integrated circuits have asymmetric clock distributions. In this paper, we propose the first CM clock synthesis (CMCS) methodology to reduce the overall clock network power with low skew. The method can integrate with traditional clock routing followed by transmitter and receiver sizing. We validate the proposed methodology using ISPD 2009 and 2010 industrial benchmarks using an extracted SPICE model distributed in 1.4–275.6-mm2 area and consists of 81–2249 sinks. This methodology saves 39%–84% average power with similar skew on the benchmarks using 45-nm CMOS technology simulation of clock frequencies range from 1–3 GHz. In addition, the CMCS methodology takes $2.4-9.1\times $ less running time and consumes 20%–26% less transistor area compared with synthesized, buffered VM clock distributions. [ABSTRACT FROM PUBLISHER] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2016.2605580 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 9 StartPage: 1054 Subjects: – SubjectFull: Clock distribution networks Type: general – SubjectFull: Current-mode circuits Type: general – SubjectFull: Low voltage integrated circuits Type: general Titles: – TitleFull: CMCS: Current-Mode Clock Synthesis. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Islam, Riadul – PersonEntity: Name: NameFull: Guthaus, Matthew R. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: Mar2017 Type: published Y: 2017 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 25 – Type: issue Value: 3 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
| ResultId | 1 |
