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The Investigation and Optimisation of Phase-Induced Amplitude Attenuation in the Injection-Locked Ring Oscillators-Based Receiver.

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Title: The Investigation and Optimisation of Phase-Induced Amplitude Attenuation in the Injection-Locked Ring Oscillators-Based Receiver.
Authors: Yu, Xiao1 xpyu@vlsi.zju.edu.cn, Liu, Zhe1 liuzhe@vlsi.zju.edu.cn, Fan, De fdz_zju@163.com, Yeo, Kiat2 kiatseng_yeo@sutd.edu.sg
Source: Circuits, Systems & Signal Processing. May2017, Vol. 36 Issue 5, p1818-1835. 18p.
Subjects: Injection locked oscillators, Sensitivity analysis, Telecommunication systems, CMOS memory circuits, Energy consumption, Sound-wave attenuation
Abstract: In this paper, the injection-locked oscillator (ILO)-based receiver is investigated. The key design considerations of the ILO including the phase difference between the input and output signals and its impact on the ILO-based receiver are analysed in detail. Different strategies for both the narrow and wide-band applications are discussed and simulated. As a design example, a 2.4 GHz ILO-based receiver is implemented using a standard 40 nm CMOS technology, where a three-stage inverter-based ILO is optimised to maintain a good balance among working range, sensitivity and power consumption, etc. Measurement results show that the proposed receiver is able to demodulate an input signal at a 2.4 GHz carrier frequency with the data rate up to 1 Mbps while consuming $${<}300\, \upmu \hbox {W}$$ power. It is suitable for short-range communication system such as chip-scale data link. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:In this paper, the injection-locked oscillator (ILO)-based receiver is investigated. The key design considerations of the ILO including the phase difference between the input and output signals and its impact on the ILO-based receiver are analysed in detail. Different strategies for both the narrow and wide-band applications are discussed and simulated. As a design example, a 2.4 GHz ILO-based receiver is implemented using a standard 40 nm CMOS technology, where a three-stage inverter-based ILO is optimised to maintain a good balance among working range, sensitivity and power consumption, etc. Measurement results show that the proposed receiver is able to demodulate an input signal at a 2.4 GHz carrier frequency with the data rate up to 1 Mbps while consuming $${<}300\, \upmu \hbox {W}$$ power. It is suitable for short-range communication system such as chip-scale data link. [ABSTRACT FROM AUTHOR]
ISSN:0278081X
DOI:10.1007/s00034-016-0405-5